T. Irisawa, K. Ikeda, Y. Moriyama, M. Oda, E. Mieda, T. Maeda, T. Tezuka
{"title":"Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate","authors":"T. Irisawa, K. Ikeda, Y. Moriyama, M. Oda, E. Mieda, T. Maeda, T. Tezuka","doi":"10.1109/VLSIT.2014.6894395","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894395","url":null,"abstract":"An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117283381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Liu, M. Chi, Anurag Mittal, G. Aluri, S. Uppal, P. Paliwoda, E. Banghart, K. Korablev, B. Liu, M. Nam, M. Eller, S. Samavedam
{"title":"Anti-fuse memory array embedded in 14nm FinFET CMOS with novel selector-less bit-cell featuring self-rectifying characteristics","authors":"Y. Liu, M. Chi, Anurag Mittal, G. Aluri, S. Uppal, P. Paliwoda, E. Banghart, K. Korablev, B. Liu, M. Nam, M. Eller, S. Samavedam","doi":"10.1109/VLSIT.2014.6894356","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894356","url":null,"abstract":"A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents the sneak current in the cross-point array, therefore no need for select transistor in each cell. Thus enables the smallest reported bit-cell with area measuring 0.036 μm2.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115139067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ueda, Seungmin Jung, T. Mizutani, Ashok Kumar, T. Saraya, T. Hiramoto
{"title":"Ultra-low voltage (0.1V) operation of Vth self-adjusting MOSFET and SRAM cell","authors":"A. Ueda, Seungmin Jung, T. Mizutani, Ashok Kumar, T. Saraya, T. Hiramoto","doi":"10.1109/VLSIT.2014.6894416","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894416","url":null,"abstract":"A V<sub>th</sub> self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the V<sub>th</sub> self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated. In this device, V<sub>th</sub> automatically decreases at on-state and increases at off-state, resulting in high I<sub>on</sub>/I<sub>off</sub> ratio as well as stable SRAM operation at low V<sub>dd</sub>. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with V<sub>th</sub> self-adjusting nFETs and pFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128498872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Weber, E. Josse, F. Andrieu, A. Cros, E. Richard, P. Perreau, E. Baylac, N. Degors, C. Gallon, E. Perrin, S. Chhun, E. Petitprez, S. DelMedico, J. Simon, G. Druais, S. Lasserre, J. Mazurier, N. Guillot, É. Bernard, R. Bianchini, L. Parmigiani, X. Gérard, C. Pribat, O. Gourhant, F. Abbate, C. Gaumer, V. Beugin, P. Gouraud, P. Maury, S. Lagrasta, D. Barge, N. Loubet, R. Beneyton, D. Benoit, S. Zoll, J. Chapon, L. Babaud, M. Bidaud, M. Grégoire, C. Monget, B. Le-Gratiet, P. Brun, M. Mellier, A. Pofelski, L. Clément, R. Bingert, S. Puget, J. Kruck, D. Hoguet, P. Scheer, T. Poiroux, J. Manceau, M. Rafik, D. Rideau, M. Jaud, J. Lacord, F. Monsieur, L. Grenouillet, M. Vinet, Q. Liu, B. Doris, M. Celik, S. Fetterolf, O. Faynot, M. Haond
{"title":"14nm FDSOI technology for high speed and energy efficient applications","authors":"O. Weber, E. Josse, F. Andrieu, A. Cros, E. Richard, P. Perreau, E. Baylac, N. Degors, C. Gallon, E. Perrin, S. Chhun, E. Petitprez, S. DelMedico, J. Simon, G. Druais, S. Lasserre, J. Mazurier, N. Guillot, É. Bernard, R. Bianchini, L. Parmigiani, X. Gérard, C. Pribat, O. Gourhant, F. Abbate, C. Gaumer, V. Beugin, P. Gouraud, P. Maury, S. Lagrasta, D. Barge, N. Loubet, R. Beneyton, D. Benoit, S. Zoll, J. Chapon, L. Babaud, M. Bidaud, M. Grégoire, C. Monget, B. Le-Gratiet, P. Brun, M. Mellier, A. Pofelski, L. Clément, R. Bingert, S. Puget, J. Kruck, D. Hoguet, P. Scheer, T. Poiroux, J. Manceau, M. Rafik, D. Rideau, M. Jaud, J. Lacord, F. Monsieur, L. Grenouillet, M. Vinet, Q. Liu, B. Doris, M. Celik, S. Fetterolf, O. Faynot, M. Haond","doi":"10.1109/VLSIT.2014.6894343","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894343","url":null,"abstract":"This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m2 high-density bitcell and two 0.090°m2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124077141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Dong, X. Wang, J. Zhang, X. Li, X. Lou, N. Conrad, H. Wu, R. Gordon, P. Ye
{"title":"III–V CMOS devices and circuits with high-quality atomic-layer-epitaxial La2O3/GaAs interface","authors":"L. Dong, X. Wang, J. Zhang, X. Li, X. Lou, N. Conrad, H. Wu, R. Gordon, P. Ye","doi":"10.1109/VLSIT.2014.6894361","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894361","url":null,"abstract":"By realizing a high-quality epitaxial La2O3/ GaAs(111)A interface, we demonstrate GaAs CMOS devices and integrated circuits including nMOSFETs, pMOSFETs, CMOS inverters, NAND and NOR logic gates and five-stage ring oscillators for the first time. As an exercise of III-V CMOS circuits on a common substrate with a common gate dielectric, it provides a route to realize ultimate high-mobility CMOS on Si if long-time expected breakthroughs of III-V epi-growth on Si occur.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134400428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, T. Schram, R. Ritzenthaler, A. Thean, G. Groeseneken, A. Asenov
{"title":"Time-dependent variation: A new defect-based prediction methodology","authors":"M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, T. Schram, R. Ritzenthaler, A. Thean, G. Groeseneken, A. Asenov","doi":"10.1109/VLSIT.2014.6894373","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894373","url":null,"abstract":"For the first time, different impacts of as-grown and generated defects on nm-sized devices are demonstrated. As-grown hole traps are responsible for WDF, which increases with Vg_op and tw. The generated defects are substantial, but do not contribute to WDF and consequently are not detected by RTN. The non-discharging component follows the same model as that for large devices: the `AG' model. Based on this defect framework, a new methodology is proposed for test engineers to predict the long term TDV and yield and its prediction-capability is verified.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122924454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ho-Jung Kang, M. Jeong, S. Joe, Jihyun Seo, Sung-Kye Park, S. Jin, Byung-Gook Park, Jong-Ho Lee
{"title":"Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body","authors":"Ho-Jung Kang, M. Jeong, S. Joe, Jihyun Seo, Sung-Kye Park, S. Jin, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/VLSIT.2014.6894348","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894348","url":null,"abstract":"We characterized the behavior of transient bit-line current (IBL) during reading after giving a pre-bias (Vpre) to two different cells in 3-D stacked NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in blocking dielectric or the interface between the tunneling oxide and the poly-Si body, opposite behavior was observed. To identify the cause, we systematically analyzed the capture and emission of charges in two trap sites by investigating transient IBL behaviors during reading with various Vpres and fast & pulsed I-Vs. The carrier life time and trap density associated with grain size were extracted to substantiate different trap density with the vertical position of cells.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127767095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Lien, Zhen-Kai Kuo, Teng-Han Huang, Y. Liao, Si-Chen Lee, Hau He
{"title":"Paper memory by all printing technology","authors":"D. Lien, Zhen-Kai Kuo, Teng-Han Huang, Y. Liao, Si-Chen Lee, Hau He","doi":"10.1109/VLSIT.2014.6894364","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894364","url":null,"abstract":"We report the first paper-based nonvolatile memory device by means of an all-printing approach using a sequence of inkjet and screen printing techniques to fabricate a resistive random access memory on paper. The printed paper-based memory devices (PPMDs) can be labeled on electronics or living objects for multi-functional, wearable, on-skin, and biocompatible applications. The PPMDs would be a key electronic component to fully activate a paper-based circuit and can be directly implemented in medical biosensors, multi-functional devices, and self-powered systems.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116766295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Lung, M. BrightSky, W. Chien, J. Y. Wu, S. Kim, W. Kim, H. Cheng, Y. Zhu, T. Wang, R. Cheek, R. Bruce, C. Lam
{"title":"Towards the integration of both ROM and RAM functions phase change memory cells on a single die for system-on-chip (SOC) applications","authors":"H. Lung, M. BrightSky, W. Chien, J. Y. Wu, S. Kim, W. Kim, H. Cheng, Y. Zhu, T. Wang, R. Cheek, R. Bruce, C. Lam","doi":"10.1109/VLSIT.2014.6894383","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894383","url":null,"abstract":"We discovered that by changing the dielectric capping layer above the phase change memory element we can change the SET speed and data retention of the memory. This allows us, for the first time, to integrate memories of different functions on the same chip with simple processes. By using a low temperature silicon nitride capping material we can get fast SET speed down to 20ns. With a high temperature silicon nitride capping material, on the other hand, data retention is increased to > 400 years at 85°C. Based on these discoveries, we propose a unified embedded memory solution which provides both ROM and RAM functions in a single chip for SOC applications.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. W. Lu, C. Vaz, J. Campbell, J. Ryan, K. Cheung, G. Jiao, G. Bersuker, C. Young
{"title":"Device-level PBTI-induced timing jitter increase in circuit-speed random logic operation","authors":"J. W. Lu, C. Vaz, J. Campbell, J. Ryan, K. Cheung, G. Jiao, G. Bersuker, C. Young","doi":"10.1109/VLSIT.2014.6894387","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894387","url":null,"abstract":"We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar increases in random timing jitter. This calls into question the widely assumed degradation headroom between DC and AC measurements. This work collectively provides a snapshot of PBTI degradation in “real” circuit environments. It provides a path for more accurate and realistic circuit lifetime estimations and circuit timing budget criteria.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116765485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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