Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body

We characterized the behavior of transient bit-line current (IBL) during reading after giving a pre-bias (Vpre) to two different cells in 3-D stacked NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in blocking dielectric or the interface between the tunneling oxide and the poly-Si body, opposite behavior was observed. To identify the cause, we systematically analyzed the capture and emission of charges in two trap sites by investigating transient IBL behaviors during reading with various Vpres and fast & pulsed I-Vs. The carrier life time and trap density associated with grain size were extracted to substantiate different trap density with the vertical position of cells.