14nm FDSOI technology for high speed and energy efficient applications

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI:10.1109/VLSIT.2014.6894343

O. Weber, E. Josse, F. Andrieu, A. Cros, E. Richard, P. Perreau, E. Baylac, N. Degors, C. Gallon, E. Perrin, S. Chhun, E. Petitprez, S. DelMedico, J. Simon, G. Druais, S. Lasserre, J. Mazurier, N. Guillot, É. Bernard, R. Bianchini, L. Parmigiani, X. Gérard, C. Pribat, O. Gourhant, F. Abbate, C. Gaumer, V. Beugin, P. Gouraud, P. Maury, S. Lagrasta, D. Barge, N. Loubet, R. Beneyton, D. Benoit, S. Zoll, J. Chapon, L. Babaud, M. Bidaud, M. Grégoire, C. Monget, B. Le-Gratiet, P. Brun, M. Mellier, A. Pofelski, L. Clément, R. Bingert, S. Puget, J. Kruck, D. Hoguet, P. Scheer, T. Poiroux, J. Manceau, M. Rafik, D. Rideau, M. Jaud, J. Lacord, F. Monsieur, L. Grenouillet, M. Vinet, Q. Liu, B. Doris, M. Celik, S. Fetterolf, O. Faynot, M. Haond

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引用次数: 85

Abstract

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m2 high-density bitcell and two 0.090°m2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

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14nm FDSOI技术，适用于高速和节能应用

本文介绍了一种用于应变工程FDSOI晶体管高速节能应用的14nm技术。与28nm FDSOI技术相比，14nm FDSOI技术提供了0.55倍的面积缩放，并在相同功率下提供了30%的速度提升，或者在相同速度下降低55%的功率，这是由于驱动电流的增加和栅极-漏极电容的降低。使用正向反向偏置(FBB)，我们通过实验证明，该技术的功率效率为以相同速度工作的环形振荡器提供了额外40%的动态功率降低。最后，报告了一个完整的单端口SRAM产品，包括一个0.081°m2的高密度位单元和两个0.090°m2的位单元，用于解决高性能和低泄漏-低Vmin要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

CiteScore

3.40

自引率

0.00%

发文量