2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers最新文献

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Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s Sub-100 nm再生S/D栅极- last In0.7Ga0.3As QW mosfet, μn,eff > 5,500 cm2/V-s
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894351
C. Shin, W. Park, S. Shin, Y. D. Cho, D. Ko, T. Kim, D. Koh, H. Kwon, R. Hill, P. Kirsch, W. Maszara, D. Kim
{"title":"Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s","authors":"C. Shin, W. Park, S. Shin, Y. D. Cho, D. Ko, T. Kim, D. Koh, H. Kwon, R. Hill, P. Kirsch, W. Maszara, D. Kim","doi":"10.1109/VLSIT.2014.6894351","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894351","url":null,"abstract":"This paper reports on gate-last (GL) In<sub>0.7</sub>Ga<sub>0.3</sub>As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μ<sub>n,eff</sub>>5,500 cm<sup>2</sup>/V-s at 300k). Short-channel device with L<sub>g</sub> = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with g<sub>m_max</sub> = 2 mS/μm at V<sub>DS</sub> = 0.5 V. This record performance is achieved by using a low D<sub>it</sub> and Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> gate stack with EOT ~ 1-nm, optimized selective S/D regrowth with MOCVD, and GL process.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor's performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design 通过新的磁栅堆叠方案设计,在Ge (100) n- fet上展示了具有Jg-EOT良好特性的巨大磁电容和“负”电容效应以及晶体管的性能
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894375
M. Liao, S. C. Huang, C. Y. Liu, P. G. Chen, S. Kao, C. Lien
{"title":"The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor's performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design","authors":"M. Liao, S. C. Huang, C. Y. Liu, P. G. Chen, S. Kao, C. Lien","doi":"10.1109/VLSIT.2014.6894375","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894375","url":null,"abstract":"Super Jg-EOT gate stack characteristics, ultra-high κ value, and the promising transistor's performance are achieved on the Ge n-FET by the application of the BaTiO3 as the gate dielectric and the magnetic FePt film as the metal gate. The super Cgate/κ-value is generated by more dipoles in the HK dielectric layer with the coupling of the build-in magnetic field from MG (HK: BaTiO3; MG: magnetic FePt). With the demonstration of this classical “colossal magneto-capacitance” effect in this work, the κ value can be improved ~175% successfully together with the reduction of Jg ~100X and the Ion is improved ~50% accordingly. On the other hand, the “negative” capacitance effect, which is important for the future steeper sub-threshold swing (S.S) device design, is also observed. The novel gate stack scheme (BaTiO3 HK+ FePt MG), proposed in this work, with the super Jg-EOT characteristics, “negative” capacitance phenomenon, and the promising transistor's performance on the high mobility (Ge) material provides the useful solution for the future low power mobile device design.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process induced variations 高性能移动SoC设计和技术协同优化,以减轻高k金属栅极工艺引起的变化
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894381
Sam Yang, L. Ge, Jeff Lin, M. Han, Dang-qiang Yang, Joseph Wang, Kasim H. Mahmood, Tony Song, D. Yuan, Dongwon Seo, M. Pedrali-Noy, D. Alladi, Sameer Wadhwa, Xiaoliang Bai, Liang Dai, S. Yoon, E. Terzioglu, S. Bazarjani, G. Yeap
{"title":"High performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process induced variations","authors":"Sam Yang, L. Ge, Jeff Lin, M. Han, Dang-qiang Yang, Joseph Wang, Kasim H. Mahmood, Tony Song, D. Yuan, Dongwon Seo, M. Pedrali-Noy, D. Alladi, Sameer Wadhwa, Xiaoliang Bai, Liang Dai, S. Yoon, E. Terzioglu, S. Bazarjani, G. Yeap","doi":"10.1109/VLSIT.2014.6894381","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894381","url":null,"abstract":"Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131433621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Investigation of InxGa1−xAs FinFET architecture with varying indium (x) concentration and quantum confinement 不同铟(x)浓度和量子约束下InxGa1−xAs FinFET结构的研究
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894372
V. Arun, N. Agrawal, G. Lavallee, M. Cantoro, Sang-Su Kim, Dong-Won Kim, S. Datta
{"title":"Investigation of InxGa1−xAs FinFET architecture with varying indium (x) concentration and quantum confinement","authors":"V. Arun, N. Agrawal, G. Lavallee, M. Cantoro, Sang-Su Kim, Dong-Won Kim, S. Datta","doi":"10.1109/VLSIT.2014.6894372","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894372","url":null,"abstract":"In<sub>x</sub>Ga<sub>1-x</sub>As FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In<sub>0.7</sub>Ga<sub>0.3</sub>As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm<sup>2</sup>/V-sec at a fin width of 38nm with highest performance. Short channel In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFF (L<sub>g</sub>=120nm) exhibits I<sub>DSAT</sub> of 1.16mA/μm at V<sub>G</sub>-V<sub>T</sub>=1V and extrinsic peak g<sub>m</sub>=1.9mS/μm at V<sub>DS</sub>=0.5V and I<sub>OFF</sub>=30 nA/μm. Components of external resistance (R<sub>Ext</sub>), side wall DIT, fin profile are analyzed to investigate feasibility of In<sub>x</sub>Ga<sub>1-x</sub>As FinFET for beyond 10nm technology node.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
III–V single structure CMOS by using ultrathin body InAs/GaSb-OI channels on Si 采用超薄体InAs/GaSb-OI通道的III-V单结构CMOS
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894350
M. Yokoyama, H. Yokoyama, M. Takenaka, S. Takagi
{"title":"III–V single structure CMOS by using ultrathin body InAs/GaSb-OI channels on Si","authors":"M. Yokoyama, H. Yokoyama, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2014.6894350","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894350","url":null,"abstract":"We propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). We experimentally demonstrate both n- and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134072542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Customer value creation in the information explosion era 信息爆炸时代的客户价值创造
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894340
Keiichiro Shimada
{"title":"Customer value creation in the information explosion era","authors":"Keiichiro Shimada","doi":"10.1109/VLSIT.2014.6894340","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894340","url":null,"abstract":"The present-day information explosion era in combination with modern semiconductor technology have had a great impact on consumer electronics and information industries. The progress of semiconductor technology and information transmission technology under Moore's Law has eased various constraints on customers, such as place, time, and required preparations. The television, the video recorder, and on-demand broadcasting are three key technologies that have helped overcome these constraints and create new customer values. The amount of communication is still rapidly growing due to the explosion of data contents (such as 4K image) and data creators (such as CGM and IoT). This trend will create new customer values and have a huge impact on semiconductor technology and fabrication.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The demonstration of D-SMT stressor on Si and Ge n-FinFETs D-SMT应力源在Si和Ge n- finfet上的演示
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894424
M. Liao, P. G. Chen, S. C. Huang, S. Kao, C. X. Hung, K. Liu, C. Lien, C. Y. Liu
{"title":"The demonstration of D-SMT stressor on Si and Ge n-FinFETs","authors":"M. Liao, P. G. Chen, S. C. Huang, S. Kao, C. X. Hung, K. Liu, C. Lien, C. Y. Liu","doi":"10.1109/VLSIT.2014.6894424","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894424","url":null,"abstract":"The ~20% Id,sat improvement is demonstrated successfully on the Si and Ge n-FinFETs with the implement of D-SMT stressor for the first time, based on the optimization of dislocation angle and the understanding of crystal re-growth velocities along different surface planes and directions in Si and Ge. The mobility enhancement ratio with D-SMT stressor in Ge n-FinFET (37%) is found to be larger than it in the Si n-FinFET (30%). Ultra-high capping stress film (>3 GPa) is needed and is the must to modify the crystal re-growth velocities along the [100] and [110] directions for the dislocation angle optimization and the implement of D-SMT on the FinFET structure. The larger stress and mobility enhancement ratio are observed in the narrower gate width device, due to the effect of triple crystal re-growth directions on the FinFET structure. Finally, the mobility enhancement ratio with the stress on the Si (100)/[110], Si (110)/[110], Ge (100)/[110] and Ge (110)/[110] is calculated theoretically and further discussed.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134427135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling 低损耗硅中间体三维系统集成与嵌入式微流控冷却
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894399
Paragkumar Thadesar, Li Zheng, M. Bakir
{"title":"Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling","authors":"Paragkumar Thadesar, Li Zheng, M. Bakir","doi":"10.1109/VLSIT.2014.6894399","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894399","url":null,"abstract":"Novel technology enablers for high-performance three-dimensional (3D) system integration are demonstrated in this paper: (a) A thick silicon interposer with 65 μm diameter and 370 μm tall low-loss polymer-embedded vias on a 150 μm pitch is fabricated and characterized demonstrating a 78% reduction in insertion loss compared to similar-sized conventional TSVs at 50 GHz; (b) Two dice with embedded microfluidic heatsinks and electrical and fluidic microbumps are assembled to an interposer demonstrating lower thermal resistance, chip-to-interposer average electrical microbump resistance of 12.06 mΩ and a robust fluidic microbump interconnection.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories 演示全功能8Mb垂直STT-MRAM芯片,写入低于5ns,用于非易失性嵌入式存储器
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894357
G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, R. Tong, K. Pi, Yu-Jen Wang, D. Shen, R. He, J. Haq, J. Teng, V. Lam, K. Huang, T. Zhong, T. Torng, P. Wang
{"title":"Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories","authors":"G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, R. Tong, K. Pi, Yu-Jen Wang, D. Shen, R. He, J. Haq, J. Teng, V. Lam, K. Huang, T. Zhong, T. Torng, P. Wang","doi":"10.1109/VLSIT.2014.6894357","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894357","url":null,"abstract":"We present major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°C for 1 hour. We have successfully integrated the novel structure onto an 8Mbit test chip. We demonstrate writing of every single cell in the array using sub-5ns pulses over a wide temperature range without using any error correction. We also show that sensing times of 4ns are sufficient to read every data cell. The inherent scalability of the design makes it a prime candidate for universal embedded non-volatile memories down to the 28nm node and beyond.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132805648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics 用于7nm finfet的第四组通道:soc功率和速度指标的性能
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894380
M. Bardon, P. Raghavan, G. Eneman, P. Schuddinck, M. Dehan, A. Mercha, A. Thean, D. Verkest, A. Steegen
{"title":"Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics","authors":"M. Bardon, P. Raghavan, G. Eneman, P. Schuddinck, M. Dehan, A. Mercha, A. Thean, D. Verkest, A. Steegen","doi":"10.1109/VLSIT.2014.6894380","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894380","url":null,"abstract":"Smart Mobile SoCs combine the need for speed and for power efficiency. For the 7nm node, high-mobility materials (SiGe, Ge, and IIIV) are candidates to replace Si channels and continue speed improvement, but are more prone to leakage currents impacting active leakage power. Transport and voltages at scaled dimensions could also influence the benefit of higher mobility. We evaluate these aspects for group IV channels devices in the SoC context using an holistic approach over energy-delay metrics and in a node to node perspective. At the 7nm node, Ge devices are expected to reach 34% improvement in frequency at Vdd of 0.65V assuming a series resistance of 230 Ω-um can be reached. Low power complementary Si devices are needed to meet the active leakage budget of mobile SoCs.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133392542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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