C. Shin, W. Park, S. Shin, Y. D. Cho, D. Ko, T. Kim, D. Koh, H. Kwon, R. Hill, P. Kirsch, W. Maszara, D. Kim
{"title":"Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s","authors":"C. Shin, W. Park, S. Shin, Y. D. Cho, D. Ko, T. Kim, D. Koh, H. Kwon, R. Hill, P. Kirsch, W. Maszara, D. Kim","doi":"10.1109/VLSIT.2014.6894351","DOIUrl":null,"url":null,"abstract":"This paper reports on gate-last (GL) In<sub>0.7</sub>Ga<sub>0.3</sub>As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μ<sub>n,eff</sub>>5,500 cm<sup>2</sup>/V-s at 300k). Short-channel device with L<sub>g</sub> = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with g<sub>m_max</sub> = 2 mS/μm at V<sub>DS</sub> = 0.5 V. This record performance is achieved by using a low D<sub>it</sub> and Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> gate stack with EOT ~ 1-nm, optimized selective S/D regrowth with MOCVD, and GL process.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894351","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper reports on gate-last (GL) In0.7Ga0.3As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μn,eff>5,500 cm2/V-s at 300k). Short-channel device with Lg = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with gm_max = 2 mS/μm at VDS = 0.5 V. This record performance is achieved by using a low Dit and Al2O3/HfO2 gate stack with EOT ~ 1-nm, optimized selective S/D regrowth with MOCVD, and GL process.