2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers最新文献_第5页

Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond 用于14纳米及以上的FinFET替代金属栅极的简单栅极金属退火(SIGMA)堆栈

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894358

T. Ando, B. Kannan, U. Kwon, W. Lai, B. Linder, E. Cartier, R. Haight, M. Copel, J. Bruley, S. Krishnan, V. Narayanan

引用次数: 12

Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications 面向3D NAND闪存应用的表面控制超薄(2nm)多晶硅通道无结场效应晶体管

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894385

Jong Kyung Park, Seung-Yoon Kim, Ki-hong Lee, S. Pyi, Seok-Hee Lee, B. Cho

引用次数: 14

1T-1R pillar-type topological-switching random access memory (TRAM) and data retention of GeTe/Sb2Te3 super-lattice films 1T-1R柱型拓扑开关随机存取存储器(TRAM)和GeTe/Sb2Te3超晶格薄膜的数据保留

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894436

M. Tai, T. Ohyanagi, M. Kinoshita, T. Morikawa, K. Akita, S. Kato, H. Shirakawa, M. Araidai, K. Shiraishi, N. Takaura

引用次数: 15

What can we do about barrier layer scaling to 5 nm node technology ? 我们如何将势垒层扩展到5nm节点技术?

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894408

J. Koike

引用次数: 1

Novel Critical Path Aware transistor optimization for mobile SoC device-circuit co-design 面向移动SoC器件电路协同设计的新型关键路径感知晶体管优化

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894379

N. Mojumder, S. C. Song, Joseph Wang, K. Lin, K. Rim, Jeff Xu, G. Yeap

引用次数: 2

Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond 20nm/16nm及以上工艺，采用质量回流和热压缩键合组装工艺与细间距铜柱凸点的芯片封装相互作用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894412

Lily Zhao, A. Bao, YangYang Sun, Chun-Jen Chen, S. Tsai, Kenny Lee, Xuefeng Zhang, D. Perry, Tor Kalleberg, M. Han, S. Bezuk, G. Yeap

引用次数: 2

Undoped Ge0.92Sn0.08 quantum well PMOSFETs on (001), (011) and (111) substrates with in situ Si2H6 passivation: High hole mobility and dependence of performance on orientation 在原位Si2H6钝化(001)、(011)和(111)衬底上未掺杂Ge0.92Sn0.08量子阱pmosfet:高空穴迁移率和性能依赖于取向

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894376

Mingshan Liu, G. Han, Yan Liu, Chunfu Zhang, Hongjuan Wang, Xiangdong Li, Jincheng Zhang, B. Cheng, Y. Hao

引用次数: 24

Device and technology implications of the Internet of Things 物联网的设备和技术影响

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894339

R. Aitken, V. Chandra, James Myers, Bal Sandhu, L. Shifren, G. Yeric

引用次数: 65

A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL 具有亚μm间距Cu RDL的高性能低成本片上封装

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894398

W. Liao, C. C. Chiang, Wei Wu, C. Fan, S. Chiu, C. Chiu, T. Chen, C. Hsieh, H. Y. Chen, H. Y. Lo, L. Huang, T. J. Wu, W. Chiou, S. Hou, S. Jeng, Yue Doug

{"title":"A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL","authors":"W. Liao, C. C. Chiang, Wei Wu, C. Fan, S. Chiu, C. Chiu, T. Chen, C. Hsieh, H. Y. Chen, H. Y. Lo, L. Huang, T. J. Wu, W. Chiou, S. Hou, S. Jeng, Yue Doug","doi":"10.1109/VLSIT.2014.6894398","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894398","url":null,"abstract":"A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8μm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated from good continuity of long RDL chains. Two layers of backside RDL are used to redistribute the IO from TSV at 0.2 mm pitch to BGA at 0.6 mm pitch. With the same multi-die integration capability as in CoWoS™, the CoW package has additional advantages of lower z-height, better thermal dissipation, and lower cost. Moreover, mechanical and thermal simulations reveal a relatively greater life cycle endurance for temperature cycling on board (TCoB) test. The CoW package passed preliminary component-level reliability assessments including μHAST, HTS and TC. This provides a promising CoWoS™ alternative for lower cost and thinner package with improved thermal performance. It also possesses the flexibility to combine with fan-out technology to be fitted in applications requiring higher IO count or larger BGA pitch.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Integration of silicon photonics in bulk CMOS 硅光子学在体CMOS中的集成

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894427

Roy Meade, J. Orcutt, K. Mehta, Ofer Tehar-Zahav, Daniel L. Miller, M. Georgas, B. Moss, Chen Sun, Yu-hsin Chen, J. Shainline, M. Wade, R. Bafrali, Zvi Sternberg, G. Machavariani, G. Sandhu, M. Popović, Rajeev J Ram, V. Stojanović

引用次数: 20