2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers最新文献_第6页

In0.53Ga0.47As quantum-well MOSFET with source/drain regrowth for low power logic applications In0.53Ga0.47As源极/漏极再生量子阱MOSFET，用于低功耗逻辑应用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894419

X. Zhou, A. Alian, Y. Mols, R. Rooyackers, G. Eneman, D. Lin, T. Ivanov, A. Pourghaderi, N. Collaert, A. Thean

引用次数: 9

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era 面向物联网时代高能效电子产品的薄埋氧化硅(SOTB) CMOS超低电压设计与技术

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894413

S. Kamohara, N. Sugii, Yoshiki Yamamoto, H. Makiyama, T. Yamashita, T. Hasegawa, S. Okanishi, H. Yanagita, M. Kadoshima, K. Maekawa, H. Mitani, Y. Yamagata, H. Oda, Y. Yamaguchi, K. Ishibashi, H. Amano, K. Usami, Kazutoshi Kobayashi, T. Mizutani, T. Hiramoto

{"title":"Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era","authors":"S. Kamohara, N. Sugii, Yoshiki Yamamoto, H. Makiyama, T. Yamashita, T. Hasegawa, S. Okanishi, H. Yanagita, M. Kadoshima, K. Maekawa, H. Mitani, Y. Yamagata, H. Oda, Y. Yamaguchi, K. Ishibashi, H. Amano, K. Usami, Kazutoshi Kobayashi, T. Mizutani, T. Hiramoto","doi":"10.1109/VLSIT.2014.6894413","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894413","url":null,"abstract":"Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127086511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A novel metallic complex reaction etching for transition metal and magnetic material by low-temperature and damage-free neutral beam process for non-volatile MRAM device applications 一种用于非易失性MRAM器件的低温无损伤中性束工艺的过渡金属和磁性材料的新型金属复合反应蚀刻

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894362

X. Gu, Y. Kikuchi, T. Nozawa, S. Samukawa

引用次数: 0

Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory 50纳米c轴排列晶体In-Ga-Zn氧化物场效应晶体管的包围沟道结构及其在小于5 nsec写入速度存储器中的应用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894421

Y. Kobayashi, D. Matsubayashi, S. Nagatsuka, Y. Yakubo, T. Atsumi, Y. Shionoiri, S. Hondo, T. Yamamoto, Y. Okazaki, M. Nagai, S. Sasagawa, D. Ito, Y. Hata, T. Hamada, R. Arasawa, K. Hanaoka, M. Sakakura, H. Suzawa, Y. Yamamoto, S. Yamazaki

{"title":"Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory","authors":"Y. Kobayashi, D. Matsubayashi, S. Nagatsuka, Y. Yakubo, T. Atsumi, Y. Shionoiri, S. Hondo, T. Yamamoto, Y. Okazaki, M. Nagai, S. Sasagawa, D. Ito, Y. Hata, T. Hamada, R. Arasawa, K. Hanaoka, M. Sakakura, H. Suzawa, Y. Yamamoto, S. Yamazaki","doi":"10.1109/VLSIT.2014.6894421","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894421","url":null,"abstract":"We report novel FETs with a structure in which not only the top surface but also the side surfaces of island-shaped c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) serving as a channel are surrounded by a gate electrode, that is, surrounded channel CAAC-IGZO FETs. The FETs maintained their favorable subthreshold characteristics even if the channel length was scaled down to approximately 50 nm, i.e., normally-off, DIBL of 67 mV/V, SS of 92 mV/dec, and an off-state current lower than the measurement limit (0.1 pA) for a gate insulating film EOT of 11 nm. Moreover, we applied an FET with such a structure to a memory and discussed the writing time and the retention time, which were expected to be less than 5 ns and greater than 1,000 sec, respectively, for storage capacitance of 1 fF from circuit simulation.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132743624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce Vth & Id variability 采用10nm纳米线沟道的三栅极多晶硅mosfet的设计方法，以提高短沟道性能并降低Vth和Id可变性

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894425

M. Saitoh, K. Ota, C. Tanaka, T. Numata

引用次数: 6

A copper ReRAM cell for Storage Class Memory applications 用于存储类内存应用的铜ReRAM单元

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894368

S. Sills, Shuichiro Yasuda, Jonathan Strand, A. Calderoni, K. Aratani, A. Johnson, N. Ramaswamy

引用次数: 59

23% faster program and 40% energy reduction of carbon nanotube non-volatile memory with over 1011 endurance 程序速度提高23%，碳纳米管非易失性存储器能耗降低40%，续航时间超过1011

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894384

S. Ning, T. Iwasaki, K. Shimomura, K. Johguchi, G. Rosendale, M. Manning, Darlene Viviani, T. Rueckes, K. Takeuchi

引用次数: 11

Germanium-Tin on Silicon avalanche photodiode for short-wave infrared imaging 短波红外成像用锗锡硅雪崩光电二极管

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894428

Yuan Dong, Wei Wang, Xinran Xu, X. Gong, D. Lei, Qian Zhou, Zhe Xu, S. Yoon, G. Liang, Y. Yeo

引用次数: 6

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications 超薄至4微米，采用300毫米晶圆，经40纳米节点2Gb DRAM验证，适用于3D多堆叠WOW应用

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894347

Y. Kim, S. Kodama, Y. Mizushima, N. Maeda, H. Kitada, K. Fujimoto, T. Nakamura, D. Suzuki, A. Kawai, K. Arai, T. Ohba

引用次数: 30

Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates 通过STI (BOTS)的底部氧化-在大块衬底上制造介电隔离finfet的新方法

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers Pub Date : 2014-06-09 DOI: 10.1109/VLSIT.2014.6894390

K. Cheng, S. Seo, J. Faltermeier, D. Lu, T. Standaert, I. Ok, A. Khakifirooz, R. Vega, T. Levin, J. Li, J. Demarest, C. Surisetty, D. Song, H. Utomo, R. Chao, H. He, A. Madan, P. Dehaven, N. Klymko, Z. Zhu, S. Naczas, Y. Yin, J. Kuss, A. Jacob, D. Bae, K. Seo, W. Kleemeier, R. Sampson, T. Hook, B. Haran, G. Gifford, D. Gupta, H. Shang, H. Bu, M. Na, P. Oldiges, T. Wu, B. Doris, K. Rim, E. Nowak, R. Divakaruni, M. Khare

{"title":"Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates","authors":"K. Cheng, S. Seo, J. Faltermeier, D. Lu, T. Standaert, I. Ok, A. Khakifirooz, R. Vega, T. Levin, J. Li, J. Demarest, C. Surisetty, D. Song, H. Utomo, R. Chao, H. He, A. Madan, P. Dehaven, N. Klymko, Z. Zhu, S. Naczas, Y. Yin, J. Kuss, A. Jacob, D. Bae, K. Seo, W. Kleemeier, R. Sampson, T. Hook, B. Haran, G. Gifford, D. Gupta, H. Shang, H. Bu, M. Na, P. Oldiges, T. Wu, B. Doris, K. Rim, E. Nowak, R. Divakaruni, M. Khare","doi":"10.1109/VLSIT.2014.6894390","DOIUrl":"https://doi.org/10.1109/VLSIT.2014.6894390","url":null,"abstract":"We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125504388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14