T. Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara
{"title":"通过反向偏置具有多个Vt的最低可变性SOI finfet","authors":"T. Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara","doi":"10.1109/VLSIT.2014.6894393","DOIUrl":null,"url":null,"abstract":"FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V<sub>t</sub>) necessary for multiple V<sub>t</sub> solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I<sub>on</sub>) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V<sub>t</sub> (A<sub>Vt</sub>=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G<sub>m</sub>). Back-biasing through the SOTB provides excellent V<sub>t</sub> controllability keeping the low V<sub>t</sub> variability in contrast to V<sub>t</sub> tuning by fin channel doping.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Lowest variability SOI FinFETs having multiple Vt by back-biasing\",\"authors\":\"T. Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara\",\"doi\":\"10.1109/VLSIT.2014.6894393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V<sub>t</sub>) necessary for multiple V<sub>t</sub> solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I<sub>on</sub>) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V<sub>t</sub> (A<sub>Vt</sub>=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G<sub>m</sub>). Back-biasing through the SOTB provides excellent V<sub>t</sub> controllability keeping the low V<sub>t</sub> variability in contrast to V<sub>t</sub> tuning by fin channel doping.\",\"PeriodicalId\":105807,\"journal\":{\"name\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2014.6894393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Lowest variability SOI FinFETs having multiple Vt by back-biasing
FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.