Electrical and reliability characteristics of a scaled (∼30nm) tunnel barrier selector (W/Ta2O5/TaOx/TiO2/TiN) with excellent performance (JMAX > 107A/cm2)
J. Woo, Jeonghwan Song, Kibong Moon, Ji Hyun Lee, E. Cha, A. Prakash, Daeseok Lee, Sangheon Lee, Jaesung Park, Y. Koo, Chan Gyung Park, H. Hwang
{"title":"Electrical and reliability characteristics of a scaled (∼30nm) tunnel barrier selector (W/Ta2O5/TaOx/TiO2/TiN) with excellent performance (JMAX > 107A/cm2)","authors":"J. Woo, Jeonghwan Song, Kibong Moon, Ji Hyun Lee, E. Cha, A. Prakash, Daeseok Lee, Sangheon Lee, Jaesung Park, Y. Koo, Chan Gyung Park, H. Hwang","doi":"10.1109/VLSIT.2014.6894431","DOIUrl":null,"url":null,"abstract":"We demonstrate a selector device with excellent performances (J<sub>MAX</sub> > 10<sup>7</sup>A/cm<sup>2</sup>, switching speed <; 20ns) at the 30nm cell size. Furthermore, these promising device characteristics were achieved in a fully CMOS compatible stack (W/Ta<sub>2</sub>O<sub>5</sub>/TaO<sub>x</sub>/TiO<sub>2</sub>/TiN) with extremely thin oxide layer (<; 10nm). Through the comprehensive understanding on the exponential I-V curve, the effect of intrinsic/extrinsic factors such as scaling (area and thickness), and parasitic components were systemically investigated.","PeriodicalId":105807,"journal":{"name":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2014.6894431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
We demonstrate a selector device with excellent performances (JMAX > 107A/cm2, switching speed <; 20ns) at the 30nm cell size. Furthermore, these promising device characteristics were achieved in a fully CMOS compatible stack (W/Ta2O5/TaOx/TiO2/TiN) with extremely thin oxide layer (<; 10nm). Through the comprehensive understanding on the exponential I-V curve, the effect of intrinsic/extrinsic factors such as scaling (area and thickness), and parasitic components were systemically investigated.