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On the degradation of field-plate assisted RESURF power devices 场极板辅助复用电源器件的退化研究
2012 International Electron Devices Meeting Pub Date : 2012-12-10 DOI: 10.1109/IEDM.2012.6479036
B. Boksteen, S. Dhar, A. Ferrara, A. Heringa, R. Hueting, G. Koops, C. Salm, J. Schmitz
{"title":"On the degradation of field-plate assisted RESURF power devices","authors":"B. Boksteen, S. Dhar, A. Ferrara, A. Heringa, R. Hueting, G. Koops, C. Salm, J. Schmitz","doi":"10.1109/IEDM.2012.6479036","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479036","url":null,"abstract":"Hot-carrier degradation phenomena in field-plate assisted reduced surface field (RESURF) devices caused by high voltage off- and on-state stressing have been investigated. The device I-V characteristics are analyzed and modeled in detail. It is shown that via noninvasive low-voltage leakage characterization the surface generation velocity profiles after (high-voltage) stress can be extracted, enabling I-V degradation predictions across wide temperature ranges.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75965063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Performance comparison of III-V MOSFETs with source filter for electron energy 具有电子能量源滤波器的III-V型mosfet的性能比较
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479062
K. Lam, Y. Yeo, G. Liang
{"title":"Performance comparison of III-V MOSFETs with source filter for electron energy","authors":"K. Lam, Y. Yeo, G. Liang","doi":"10.1109/IEDM.2012.6479062","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479062","url":null,"abstract":"We evaluated the performances of two high-energy-electrons filtering MOSFET designs, the superlattice source-extension (SL) MOSFET and the p<sup>+</sup>/n<sup>+</sup> source-junction (p<sup>+</sup>n<sup>+</sup> source) MOSFET, using the sp<sup>3</sup>d<sup>5</sup>s* full-band tight-binding model, coupled with a non-equilibrium Green's function quantum transport simulator in the ballistic regime. III-V semicoductor heterojunctions made up of GaAs and In<sub>53</sub>Ga<sub>47</sub>As are investigated and the optimizing parameters such as the length of the barrier and well regions for the SL-MOSFETs and the doping concentrations and the length of n<sup>+</sup> region for the p<sup>+</sup>n<sup>+</sup> source MOSFETs are varied to understand their effects on the device performance parameters. More detailed interactions between electrons are considered in the present full-band simulations. Our optimized SL-MOSFET and p<sup>+</sup>n<sup>+</sup> source MOSFET achieve I<sub>ON</sub> = 0.81 and 0.60 mA/μm, SS = 20.9 and 23.1mV/dec@V<sub>DS</sub>=0.6V, respectively.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74295206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the microscopic origin of the frequency dependence of hole trapping in pMOSFETs pmosfet中空穴捕获频率依赖性的微观根源
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479076
T. Grasser, H. Reisinger, K. Rott, M. Toledano-Luque, B. Kaczer
{"title":"On the microscopic origin of the frequency dependence of hole trapping in pMOSFETs","authors":"T. Grasser, H. Reisinger, K. Rott, M. Toledano-Luque, B. Kaczer","doi":"10.1109/IEDM.2012.6479076","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479076","url":null,"abstract":"A detailed understanding of the physical mechanisms behind hole capture in pMOSFETs is essential for a number of reliability issues, including the negative bias temperature instability (NBTI), hot carrier degradation, random telegraph and 1/f noise. In order to better understand the controversial frequency dependence of NBTI, we study the frequency dependence of hole capture on individual defects by extending the time-dependent defect spectroscopy (TDDS) to the AC case. Conventionally, hole capture is explained by a first-order process using effective capture and emission time constants, τc and τβ. Our experimental data clearly reveals, however, that this assumption is incorrect under higher frequencies where modern digital applications typically operate. In particular, the frequency dependence visible in these effective capture times clearly confirms that hole capture must occur via an intermediate metastable state. Interestingly, the metastable state we have previously introduced to explain the DC-TDDS data also fully explains the AC-TDDS case.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73948429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs 高性能短沟道硅纳米线mosfet的室温载流子输运
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479003
A. Majumdar, S. Bangsaruntip, G. Cohen, L. Gignac, M. Guillorn, M. Frank, J. Sleight, D. Antoniadis
{"title":"Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs","authors":"A. Majumdar, S. Bangsaruntip, G. Cohen, L. Gignac, M. Guillorn, M. Frank, J. Sleight, D. Antoniadis","doi":"10.1109/IEDM.2012.6479003","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479003","url":null,"abstract":"Room-temperature carrier transport in Si nanowire (NW) MOSFETs with gate lengths and diameters down to 25 and 8 nm, respectively, is analyzed. It is shown that in Si NWs, holes exhibit channel injection and thermal velocities, as high as the highest obtained for uniaxially strained planar Si-channel electrons, likely due to combination of strain and confinement.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75092332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications 高迁移率氧化锌氮化tft，在光照偏应力条件下具有稳定的操作，适用于大面积和高分辨率显示应用
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478986
Myungkwan Ryu, Tae Sang Kim, K. Son, Hyun-Suk Kim, Joonsuk Park, Jong‐Baek Seon, Seok-Jun Seo, Sun‐Jae Kim, Eunha Lee, Hyungik Lee, S. Jeon, Seungwu Han, Sang Yoon Lee
{"title":"High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications","authors":"Myungkwan Ryu, Tae Sang Kim, K. Son, Hyun-Suk Kim, Joonsuk Park, Jong‐Baek Seon, Seok-Jun Seo, Sun‐Jae Kim, Eunha Lee, Hyungik Lee, S. Jeon, Seungwu Han, Sang Yoon Lee","doi":"10.1109/IEDM.2012.6478986","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478986","url":null,"abstract":"We have investigated material and electrical properties of ZnON based on 1st principle calculations and TFT evaluations. Theoretically, ZnON has high mobility characteristics and band-structure for high stability. Fabricated TFTs exhibited high mobility (100 cm2/Vs), good uniformity, and stable operation performance such as -2.87 V of Vth-shift under light illuminated bias-stress condition. As a new approach to overcome the performance limit of oxide-semiconductors, ZnON technology is strongly promising to achieve high mobility and operation stability required for next generation displays.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75106900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Towards direct band-to-band tunneling in P-channel tunneling field effect transistor (TFET): Technology enablement by Germanium-tin (GeSn) p沟道隧道场效应晶体管(ttfet)的直接带对带隧穿:锗锡(GeSn)技术实现
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479053
Yue Yang, S. Su, P. Guo, Wei Wang, X. Gong, Lanxiang Wang, Kain Lu Low, Guangze Zhang, C. Xue, B. Cheng, G. Han, Y. Yeo
{"title":"Towards direct band-to-band tunneling in P-channel tunneling field effect transistor (TFET): Technology enablement by Germanium-tin (GeSn)","authors":"Yue Yang, S. Su, P. Guo, Wei Wang, X. Gong, Lanxiang Wang, Kain Lu Low, Guangze Zhang, C. Xue, B. Cheng, G. Han, Y. Yeo","doi":"10.1109/IEDM.2012.6479053","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479053","url":null,"abstract":"In this work, we report the first demonstration of GeSn pTFET. Good device characteristics were obtained. This may be attributed to direct BTBT, high hole mobility in the GeSn channel, and the formation of abruptly and heavily doped N+ source. The ION performance can be improved with further device optimization.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76570165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
A Monte Carlo simulation of electron transport in Cu nano-interconnects: Suppression of resistance degradation due to LER/LWR 铜纳米互连中电子传递的蒙特卡罗模拟:LER/LWR对电阻退化的抑制
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479140
T. Kurusu, H. Tanimoto, M. Wada, A. Isobayashi, A. Kajita, N. Aoki, Y. Toyoshima
{"title":"A Monte Carlo simulation of electron transport in Cu nano-interconnects: Suppression of resistance degradation due to LER/LWR","authors":"T. Kurusu, H. Tanimoto, M. Wada, A. Isobayashi, A. Kajita, N. Aoki, Y. Toyoshima","doi":"10.1109/IEDM.2012.6479140","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479140","url":null,"abstract":"The effect of Line-Edge Roughness (LER) on electrical resistance in nanoscale Cu wires is investigated utilizing a semi-classical Monte Carlo method for simulating electron transport in metallic wires. Dependence of parameters characterizing LER such as amplitude, correlation length, and correlation between line-edges on electrical resistance is presented, and an optimal wire structure to suppress resistance degradation due to LER/LWR is discussed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80223739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The impact of assist-circuit design for 22nm SRAM and beyond 辅助电路设计对22nm及以后SRAM的影响
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479099
E. Karl, Z. Guo, Y. Ng, J. Keane, U. Bhattacharya, K. Zhang
{"title":"The impact of assist-circuit design for 22nm SRAM and beyond","authors":"E. Karl, Z. Guo, Y. Ng, J. Keane, U. Bhattacharya, K. Zhang","doi":"10.1109/IEDM.2012.6479099","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479099","url":null,"abstract":"Increasing process variation in advanced technology nodes requires sustained process and circuit innovation to meet yield, performance and margin requirements for SRAM memories. Memory assist circuits are becoming an important tool in co-developing critical scaled memory solutions and can have significant impact on process optimization, as well as power consumption, minimum operating voltage and performance of memories.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79019189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Electrostatically-reversible polarity of dual-gated graphene transistors with He ion irradiated channel: Toward reconfigurable CMOS applications 具有He离子辐照通道的双门控石墨烯晶体管的静电可逆极性:面向可重构CMOS应用
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478976
S. Nakaharai, T. Iijima, Shinich Ogawa, Shingo Suzuki, K. Tsukagoshi, S. Sato, Naoki Yokoyama
{"title":"Electrostatically-reversible polarity of dual-gated graphene transistors with He ion irradiated channel: Toward reconfigurable CMOS applications","authors":"S. Nakaharai, T. Iijima, Shinich Ogawa, Shingo Suzuki, K. Tsukagoshi, S. Sato, Naoki Yokoyama","doi":"10.1109/IEDM.2012.6478976","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478976","url":null,"abstract":"We found that a transistor with a graphene channel irradiated with He ion beams can have a transport gap of up to 380 meV. We made novel dual-gated transistors using such a channel and obtained an on-off ratio up to 103 at 200 K. This novel device has a channel region between dual gates, and the polarity of the transistor (n- or p-type) can be electrostatically reversed by simply flipping the bias polarity of one of the dual gates.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84566451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Assessment of the stochastic nature of dielectric breakdown in advanced CMOS technologies utilizing voltage ramp stress methodology 利用电压斜坡应力方法评估先进CMOS技术中介电击穿的随机性质
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479122
A. Kerber, D. Lipp, Yu-Yin Lin
{"title":"Assessment of the stochastic nature of dielectric breakdown in advanced CMOS technologies utilizing voltage ramp stress methodology","authors":"A. Kerber, D. Lipp, Yu-Yin Lin","doi":"10.1109/IEDM.2012.6479122","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479122","url":null,"abstract":"The stochastic nature of dielectric breakdown in MG/HK and poly-Si/SiON technologies is investigated. The voltage ramp stress (VRS) methodology was employed to demonstrate that the variability of the Weibull shape parameter, β·(n+1), diminishes with increasing sample size as predicted for a purely stochastic process. However, the V63 confidence limits remain essentially the same and do not follow the predictions of a purely stochastic process. It is suggested that the variability of V63 is limited by the local variations in the oxide thickness for metal gate (MG) / high-K (HK) and poly-Si/SiON technologies.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85561486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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