IET Computers and Digital Techniques最新文献_第8页

Power efficient error correction coding for on-chip interconnection links 片上互连链路的功率高效纠错编码

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-10-01 DOI: 10.1049/iet-cdt.2019.0082

Sumitra Velayudham, Sivakumar Rajagopal, Yeragudipati Venkata Ramana Rao, Seok-Bum Ko

{"title":"Power efficient error correction coding for on-chip interconnection links","authors":"Sumitra Velayudham, Sivakumar Rajagopal, Yeragudipati Venkata Ramana Rao, Seok-Bum Ko","doi":"10.1049/iet-cdt.2019.0082","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0082","url":null,"abstract":"<div>\u0000 <p>A configurable self-calibrated power efficient five-bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher-order error up to 9 bits with an error correction probability tolerance of 73% for on-chip interconnection links. Single error correction and double error detection with extended Hamming code (22,16) is utilised along with standard triplication error correction methods in the proposed code. Self-calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network-on-chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state-of-the-art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state-of-the-art works. The proposed code is more appropriate for on-chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"299-312"},"PeriodicalIF":1.2,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0082","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72137097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Ten years of hardware Trojans: a survey from the attacker's perspective 硬件木马的十年：从攻击者的角度进行的调查

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-30 DOI: 10.1049/iet-cdt.2020.0041

Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill

{"title":"Ten years of hardware Trojans: a survey from the attacker's perspective","authors":"Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill","doi":"10.1049/iet-cdt.2020.0041","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0041","url":null,"abstract":"<div>\u0000 <p>Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property vendor attacks, computer-aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field-programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti-detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"231-246"},"PeriodicalIF":1.2,"publicationDate":"2020-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2020.0041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71987479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation 基于同构消去的片上网络启发式映射NoC优化算法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-29 DOI: 10.1049/iet-cdt.2019.0212

Weng Xiaodong, Liu Yi, Yang Yintang

{"title":"Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation","authors":"Weng Xiaodong, Liu Yi, Yang Yintang","doi":"10.1049/iet-cdt.2019.0212","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0212","url":null,"abstract":"<div>\u0000 <p>With the development of network-on-chip (NoC) theory, lots of mapping algorithm have been proposed to solve the application mapping problem which is an NP-hard (non-polynomial hard) problem. Most algorithms are based on a heuristic algorithm. They are trapped by iterations limited, not by the distance between iterations, because of the isomorphism of mapping sequence. In this study, the authors define and analyse the isomorphism with the genetic algorithm (GA) which is a heuristic algorithm. Then, they proposed an approach called density direction transform algorithm to eliminate the isomorphism of mapping sequence and accelerate the convergence of population. To verify this approach, they developed a density-direction-based genetic mapping algorithm (DDGMAP) and make a comparison with genetic mapping algorithm (GMA). The experiment demonstrates that compared to the random algorithm, their algorithm (DDGMAP) can achieve on an average 23.48% delay reduction and 7.15% power reduction. And DDGMAP gets better performance than GA in searching the optimal solution.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"272-280"},"PeriodicalIF":1.2,"publicationDate":"2020-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0212","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71986614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead 基于加权前瞻的量子电路二维近邻实现技术

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2019.0257

Lalengmawia Chhangte, Alok Chakrabarty

{"title":"Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead","authors":"Lalengmawia Chhangte, Alok Chakrabarty","doi":"10.1049/iet-cdt.2019.0257","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0257","url":null,"abstract":"<div>\u0000 <p>Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubits and the swap gate insertion techniques affect the circuit cost. The authors proposed a global qubit ordering technique that considers fewer permutations for the number of interactions a qubit does with other qubits of its circuit. They also performed the local re-ordering of qubits by attempting to reduce the cost as much as possible; the cost is estimated by defining a window with weights assigned in such a way that nearby gates to the current gate in question are given higher weightage. Experiments have been conducted on NCV benchmarks, and results have been compared with those of recent state-of-the-art techniques. When compared with the existing works, the proposed method shows improvements of up to 53.3% for smaller benchmarks and up to 51.61% for larger benchmarks.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"281-289"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0257","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation 基于优化经验模式分解和非局部均值估计的实时语音增强

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2020.0034

Sagar Reddy Vumanthala, Bikshalu Kalagadda

{"title":"Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation","authors":"Sagar Reddy Vumanthala, Bikshalu Kalagadda","doi":"10.1049/iet-cdt.2020.0034","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0034","url":null,"abstract":"<div>\u0000 <p>In this study, the authors present a novel speech enhancement method by exploring the benefits of non-local means (NLM) estimation and optimised empirical mode decomposition (OEMD) adopting cubic-spline interpolation. The optimal parameters responsible for improving the performance are estimated using the path-finder algorithm. At first, the noisy speech signal is decomposed into many scaled signals called intrinsic-mode functions (IMFs) through the use of a temporary decomposition method is called sifting process in OEMD approach. The obtained IMFs are processed by NLM estimation technique in terms of non-local similarities present in each IMF, to reduce the ill-effects caused by interfering noise. The proposed NLM-based method is effective to eliminate the noise of less-frequency. Each IMF contains essential information about the signals, on some scale or frequency band. Field programmable gate array architecture is implemented on a Xilinx ISE 14.5 and the result of the proposed method offers good performance with a high signal-to-noise ratio (SNR) and low mean-square error compared to other approaches. The performance evolution is carried out for different speech signals taken from the TIMIT database and noises taken from the NOISEX-92 database in different SNR stages of 0, 5 and 10 dB, respectively.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"290-298"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2020.0034","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC 用于最小化2D和3D IC串扰的直线布线算法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2020.0010

Khokan Mondal, Subhajit Das, Tuhina Samanta

{"title":"Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC","authors":"Khokan Mondal, Subhajit Das, Tuhina Samanta","doi":"10.1049/iet-cdt.2020.0010","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0010","url":null,"abstract":"<div>\u0000 <p>The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"263-271"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2020.0010","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automated planning for finding alternative bug traces 自动规划以查找替代错误跟踪

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2019.0283

Rajib Lochan Jana, Soumyajit Dey, Arijit Mondal, Pallab Dasgupta

{"title":"Automated planning for finding alternative bug traces","authors":"Rajib Lochan Jana, Soumyajit Dey, Arijit Mondal, Pallab Dasgupta","doi":"10.1049/iet-cdt.2019.0283","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0283","url":null,"abstract":"<div>\u0000 <p>Bug traces serve as references for patching a microprocessor design after a bug has been found. Unless the root cause of a bug has been detected and patched, variants of the bug may return through alternative bug traces, following a different sequence of micro-architectural events. To avoid such a situation, the verification engineer must think of every possible way in which the bug may return, which is a complex problem for a modern microprocessor. This study proposes a methodology which gleans high-level descriptions of the micro-architectural steps and uses them in an artificial Intelligence planning framework to find alternative pathways through which a bug may return. The plans are then translated to simulation test cases which explore these potential bug scenarios. The planning tool essentially automates the task of the verification engineer towards exploring possible alternative sequences of micro-architectural steps that may allow a bug to return. The proposed methodology is demonstrated in three case studies.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"322-335"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0283","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72157106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimised HEVC encoder intra-only configuration 优化的HEVC编码器仅内部配置

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2019.0197

Nejmeddine Bahri, Randa Khemiri

{"title":"Optimised HEVC encoder intra-only configuration","authors":"Nejmeddine Bahri, Randa Khemiri","doi":"10.1049/iet-cdt.2019.0197","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0197","url":null,"abstract":"<div>\u0000 <p>High-efficiency video coding (HEVC) is the latest video coding standard aimed to reduce the bitrate by half for the same video quality compared to H.264/AVC. This encoding performance makes HEVC more suitable for high-definition video applications. However, this performance is coupled with a high-computational complexity, which makes it hard to achieve real-time video encoding with a classic embedded processor. Multicore technology of programmable processors could be a very promising solution to overcome this computational complexity. Moreover, software optimisations by proposing fast algorithms for the most complex functions could also be an efficient solution to speed up the encoding process. In this context, this study presents a fast mode decision algorithm for the intra prediction module. This algorithm aims to reduce the number of intra prediction modes to be tested instead of performing a full intra mode search. Experimental results for all-Intra configuration show that the proposed fast intra mode decision allows saving up to 46.79% of the intra prediction time in average. Encoding performance in terms of video quality and bitrate is not significantly affected.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"256-262"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0197","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Efficient VLSI architectures of lifting based 3D discrete wavelet transform 基于提升的三维离散小波变换的高效VLSI结构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2020.0038

M. Mohamed Asan Basiri

{"title":"Efficient VLSI architectures of lifting based 3D discrete wavelet transform","authors":"M. Mohamed Asan Basiri","doi":"10.1049/iet-cdt.2020.0038","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0038","url":null,"abstract":"<div>\u0000 <p>Discrete wavelet transform (DWT) is widely used in the image and video compression due to its high compression ratio and resolution. This study proposes efficient very large scale integration (VLSI) architectures of lifting based 3D-DWT using (5,3) and (9,7) Daubechies wavelets. The advantage of these proposed architectures is the absence of storage buffer in between the row, column, and temporal processes. Also, five and nine numbers of frames of the 3D signal can be processed in parallel using the proposed (5,3) and (9,7) lifting based DWTs, respectively. Due to this parallelism and the elimination of storage buffers, the throughput of the proposed design is greater than other existing techniques. The authors have implemented all the existing and proposed 3D-DWTs using 45 nm CMOS library with Cadence and Artix-7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. For example, the proposed (9,7) lifting based 3D-DWT achieves 85.4% of improvement in the throughput than the conventional design.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"247-255"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2020.0038","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture SoC上的IP集成：基于IBUS架构的高通量低成本封装器设计案例研究

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2019.0090

Xiaokun Yang, Shi Sha, Ishaq Unwala, Jiang Lu

{"title":"Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture","authors":"Xiaokun Yang, Shi Sha, Ishaq Unwala, Jiang Lu","doi":"10.1049/iet-cdt.2019.0090","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0090","url":null,"abstract":"<div>\u0000 <p>To integrate third-party intellectual properties (IPs) into a new system-on-chip (SoC) architecture is a big challenge. Therefore, this study first presents a new bus protocol named as integrated bus (IBUS), and more important, a configurable bus wrapper for connecting AXI3-interfaced IPs into IBUS is further proposed, aiming to finding the optimal balance between bus efficiency and resource cost in terms of field-programming gate array slice count, bus transfer latency, and energy consumption. As a case study, the authors implemented three IBUS wrappers for integrating three AXI3-interfaced verification IPs into an IBUS SoC. Experimental results show that their proposed work achieves a higher valid data throughput ( in the block test and in the cipher test) compared with the designs on conventional bridge-based SoC integration, as well as a large reduction in the normalised slice-time-power (18.73% in the block benchmark and 23.45% in the cipher benchmark) when setting the same weights of slice number, data transfer latency, and energy dissipation.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"353-362"},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0090","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72157107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1