{"title":"Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead","authors":"Lalengmawia Chhangte, Alok Chakrabarty","doi":"10.1049/iet-cdt.2019.0257","DOIUrl":null,"url":null,"abstract":"<div>\n <p>Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubits and the swap gate insertion techniques affect the circuit cost. The authors proposed a global qubit ordering technique that considers fewer permutations for the number of interactions a qubit does with other qubits of its circuit. They also performed the local re-ordering of qubits by attempting to reduce the cost as much as possible; the cost is estimated by defining a window with weights assigned in such a way that nearby gates to the current gate in question are given higher weightage. Experiments have been conducted on NCV benchmarks, and results have been compared with those of recent state-of-the-art techniques. When compared with the existing works, the proposed method shows improvements of up to 53.3% for smaller benchmarks and up to 51.61% for larger benchmarks.</p>\n </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 6","pages":"281-289"},"PeriodicalIF":1.1000,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0257","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/iet-cdt.2019.0257","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 4
Abstract
Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubits and the swap gate insertion techniques affect the circuit cost. The authors proposed a global qubit ordering technique that considers fewer permutations for the number of interactions a qubit does with other qubits of its circuit. They also performed the local re-ordering of qubits by attempting to reduce the cost as much as possible; the cost is estimated by defining a window with weights assigned in such a way that nearby gates to the current gate in question are given higher weightage. Experiments have been conducted on NCV benchmarks, and results have been compared with those of recent state-of-the-art techniques. When compared with the existing works, the proposed method shows improvements of up to 53.3% for smaller benchmarks and up to 51.61% for larger benchmarks.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.