IET Computers and Digital Techniques

IET Computers and Digital Techniques
期刊缩写:
IET Comput. Digital Tech.
影响因子:
1.1
ISSN:
print: 1751-8601
on-line: 1751-861X
研究领域:
工程技术-计算机:理论方法
创刊年份:
2007年
h-index:
40
自引率:
0.00%
Gold OA文章占比:
69.64%
原创研究文献占比:
100.00%
SCI收录类型:
Science Citation Index Expanded (SCIE) || Scopus (CiteScore) || Directory of Open Access Journals (DOAJ)
期刊介绍英文:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
CiteScore:
CiteScoreSJRSNIPCiteScore排名
3.50.3930.752
学科
排名
百分位
大类:Engineering
小类:Electrical and Electronic Engineering
380 / 797
52%
大类:Computer Science
小类:Hardware and Architecture
104 / 177
41%
大类:Computer Science
小类:Software
241 / 407
40%
发文信息
中科院SCI期刊分区
大类 小类 TOP期刊 综述期刊
4区 计算机科学
4区 计算机:硬件 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
4区 计算机:理论方法 COMPUTER SCIENCE, THEORY & METHODS
WOS期刊分区
学科分类
Q4COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Q3COMPUTER SCIENCE, THEORY & METHODS
历年影响因子
2015年0.5170
2016年0.5150
2017年0.6390
2018年0.8570
2019年0.8030
2020年0.8180
2021年0.9060
2022年1.2000
2023年1.1000
历年发表
2012年45
2013年38
2014年37
2015年46
2016年51
2017年33
2018年52
2019年52
2020年43
2021年39
2022年12
投稿信息
出版周期:
Bi-monthly
出版语言:
English
出版国家(地区):
ENGLAND
审稿时长:
>12 weeks
出版商:
Wiley
编辑部地址:
WILEY, 111 RIVER ST, HOBOKEN, USA, NJ, 07030-5774

IET Computers and Digital Techniques - 最新文献

A Configurable Accelerator for CNN-Based Remote Sensing Object Detection on FPGAs

Pub Date : 2024-06-20 DOI: 10.1049/2024/4415342 Yingzhao Shao, Jincheng Shang, Yunsong Li, Yueli Ding, Mingming Zhang, Ke Ren, Yang Liu

A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment

Pub Date : 2024-05-27 DOI: 10.1049/2024/7855250 Fen Ge, Guohui Zhang, Ziyu Li, Fang Zhou
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