Ying Gao, Tong Huang, Yang Jiang, Kexin Qu, Zisha Zhou, Fulei Shi
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引用次数: 0
Abstract
The rapid development of generative artificial intelligence (AI) poses new challenges to digital product copyright governance. Considering unauthorized training-data use, infringing AI-generated outputs, nonzero infringement costs, and uncertain enforcement outcomes, this paper constructs a two-population evolutionary game model between generative AI agents and digital copyright holders. The model incorporates infringement costs, probabilistic enforcement, and static and dynamic punishment mechanisms to examine the evolution of compliance, infringement, active enforcement, and passive tolerance strategies. The results show that under static punishment, the system may fall into widespread infringement, periodic oscillations, or passive tolerance. To overcome these limitations, a dynamic punishment mechanism is introduced, in which penalty intensity adjusts according to the AI side’s compliance rate. MATLAB simulations and sensitivity analyses based on normalized but industry-informed parameters verify the theoretical results. The findings indicate that dynamic punishment can improve system stability and guide periodic fluctuations toward a stable mixed–strategy equilibrium, thereby promoting a more predictable balance between AI compliance and copyright enforcement. This study provides theoretical support for adaptive copyright governance in the era of generative AI.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.