Evolutionary Game Analysis of Digital Product Copyright Protection in the Context of Generative Artificial Intelligence

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Ying Gao, Tong Huang, Yang Jiang, Kexin Qu, Zisha Zhou, Fulei Shi
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引用次数: 0

Abstract

The rapid development of generative artificial intelligence (AI) poses new challenges to digital product copyright governance. Considering unauthorized training-data use, infringing AI-generated outputs, nonzero infringement costs, and uncertain enforcement outcomes, this paper constructs a two-population evolutionary game model between generative AI agents and digital copyright holders. The model incorporates infringement costs, probabilistic enforcement, and static and dynamic punishment mechanisms to examine the evolution of compliance, infringement, active enforcement, and passive tolerance strategies. The results show that under static punishment, the system may fall into widespread infringement, periodic oscillations, or passive tolerance. To overcome these limitations, a dynamic punishment mechanism is introduced, in which penalty intensity adjusts according to the AI side’s compliance rate. MATLAB simulations and sensitivity analyses based on normalized but industry-informed parameters verify the theoretical results. The findings indicate that dynamic punishment can improve system stability and guide periodic fluctuations toward a stable mixed–strategy equilibrium, thereby promoting a more predictable balance between AI compliance and copyright enforcement. This study provides theoretical support for adaptive copyright governance in the era of generative AI.

生成式人工智能背景下数字产品版权保护的进化博弈分析
生成式人工智能的快速发展对数字产品版权治理提出了新的挑战。考虑到未经授权的训练数据使用、侵权人工智能生成的输出、非零侵权成本和不确定的执法结果,本文构建了生成型人工智能智能体与数字版权所有者之间的双种群进化博弈模型。该模型结合了侵权成本、概率执行、静态和动态惩罚机制,考察了合规、侵权、主动执行和被动容忍策略的演变。结果表明,在静态惩罚下,系统可能陷入大面积侵权、周期性振荡或被动容忍。为了克服这些限制,引入了一种动态惩罚机制,根据人工智能方的遵守率调整惩罚强度。MATLAB仿真和基于标准化但行业知情参数的灵敏度分析验证了理论结果。研究结果表明,动态惩罚可以提高系统稳定性,引导周期性波动走向稳定的混合策略均衡,从而促进人工智能合规与版权执法之间更可预测的平衡。本研究为生成式人工智能时代的适应性版权治理提供理论支持。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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