基于优化经验模式分解和非局部均值估计的实时语音增强

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Sagar Reddy Vumanthala, Bikshalu Kalagadda
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引用次数: 0

摘要

在这项研究中,作者通过探索采用三次样条插值的非局部均值(NLM)估计和优化经验模式分解(OEMD)的优点,提出了一种新的语音增强方法。使用路径查找器算法来估计负责提高性能的最佳参数。首先,通过使用一种称为OEMD方法中的筛选过程的临时分解方法,将噪声语音信号分解为许多称为本征模式函数(IMF)的缩放信号。根据每个IMF中存在的非局部相似性,通过NLM估计技术对所获得的IMF进行处理,以减少干扰噪声引起的不良影响。所提出的基于NLM的方法能够有效地消除频率较低的噪声。每个国际货币基金组织都包含关于信号的基本信息,在一定的范围或频带上。现场可编程门阵列结构在Xilinx ISE 14.5上实现,与其他方法相比,该方法具有高信噪比和低均方误差的良好性能。分别在0、5和10dB的不同SNR级中,对取自TIMIT数据库的不同语音信号和取自NOISEX-92数据库的噪声进行性能演化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation

Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation

In this study, the authors present a novel speech enhancement method by exploring the benefits of non-local means (NLM) estimation and optimised empirical mode decomposition (OEMD) adopting cubic-spline interpolation. The optimal parameters responsible for improving the performance are estimated using the path-finder algorithm. At first, the noisy speech signal is decomposed into many scaled signals called intrinsic-mode functions (IMFs) through the use of a temporary decomposition method is called sifting process in OEMD approach. The obtained IMFs are processed by NLM estimation technique in terms of non-local similarities present in each IMF, to reduce the ill-effects caused by interfering noise. The proposed NLM-based method is effective to eliminate the noise of less-frequency. Each IMF contains essential information about the signals, on some scale or frequency band. Field programmable gate array architecture is implemented on a Xilinx ISE 14.5 and the result of the proposed method offers good performance with a high signal-to-noise ratio (SNR) and low mean-square error compared to other approaches. The performance evolution is carried out for different speech signals taken from the TIMIT database and noises taken from the NOISEX-92 database in different SNR stages of 0, 5 and 10 dB, respectively.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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