基于加权前瞻的量子电路二维近邻实现技术

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Lalengmawia Chhangte, Alok Chakrabarty
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引用次数: 4

摘要

基于超导和量子点等技术的量子计算机施加了一种物理约束,要求相互作用的量子位相邻。量子位的初始位置和交换门插入技术影响电路成本。作者提出了一种全局量子位排序技术,该技术考虑了量子位与其电路中其他量子位相互作用次数的较少排列。他们还通过尝试尽可能降低成本来执行量子位的局部重新排序;通过定义具有权重的窗口来估计成本,所述权重以这样的方式分配,使得到所讨论的当前门的附近门被赋予更高的权重。在新冠病毒基准上进行了实验,并将结果与最近最先进的技术进行了比较。与现有工程相比,较小基准点和较大基准点的拟议方法分别提高了53.3%和51.61%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead

Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead

Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubits and the swap gate insertion techniques affect the circuit cost. The authors proposed a global qubit ordering technique that considers fewer permutations for the number of interactions a qubit does with other qubits of its circuit. They also performed the local re-ordering of qubits by attempting to reduce the cost as much as possible; the cost is estimated by defining a window with weights assigned in such a way that nearby gates to the current gate in question are given higher weightage. Experiments have been conducted on NCV benchmarks, and results have been compared with those of recent state-of-the-art techniques. When compared with the existing works, the proposed method shows improvements of up to 53.3% for smaller benchmarks and up to 51.61% for larger benchmarks.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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