IET Computers and Digital Techniques最新文献_第7页

An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip 基于优化骑士遍历技术的多故障检测及模块序列图的微流控生物芯片重构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-16 DOI: 10.1049/cdt2.12004

Basudev Saha, Mukta Majumder

{"title":"An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip","authors":"Basudev Saha, Mukta Majumder","doi":"10.1049/cdt2.12004","DOIUrl":"10.1049/cdt2.12004","url":null,"abstract":"<p>Conventional biomedical analysers are replaced by digital microfluidic biochips and they are adequate to integrate different biomedical functions, essential for diverse bioassay operations. From the last decade, microfluidic biochips are getting plenty of acceptances in the field of miscellaneous healthcare sectors like DNA analysis, drug discovery and clinical diagnosis. These devices are also bearing a vital role in the area of safety critical applications such as food safety testing, air quality monitoring etc. As these devices are used in safety critical applications, clinical diagnosis and real-time biomolecular assay operations, these must have properties like precision, reliability and robustness. To accept it for discriminating purposes, the microfluidic device must endorse its preciseness and strength by following sublime testing strategy. Here, an optimized droplet traversal technique is proposed to investigate the multiple defective electrodes of a digital microfluidic biochip by embedding boundary cum row traversal and KNIGHT traversal procedure (based on the famous Knight Tour Problem). The proposed approach also enumerates the traversal time for a fault-free biochip. In addition to identifying the faulty electrodes, a Module Sequencing Graph based reconfiguration technique is proposed here to reinstate the device for normal bioassay operation.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72622469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator 采用面积和功率优化的硬倍频发生器的基数8模2n乘法器

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-13 DOI: 10.1049/cdt2.12001

Naveen Kr. Kabra, Zuber M. Patel

{"title":"A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator","authors":"Naveen Kr. Kabra, Zuber M. Patel","doi":"10.1049/cdt2.12001","DOIUrl":"10.1049/cdt2.12001","url":null,"abstract":"<p>The moduli 2<sup><i>n</i></sup> multiplier plays a vital role in the design of a residue number system processor. When the radix-8 booth-encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2<sup><i>n</i></sup> multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈<i>log</i><sub>2</sub><i>n</i>⌉-2 prefix levels and total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit-45 nm technology. The post-synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post-layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post-layout result of modulo 2<sup><i>n</i></sup>multiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78496049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fragmented software-based self-test technique for online intermittent fault detection in processors 基于碎片化软件的处理器间歇故障在线自检技术

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-13 DOI: 10.1049/cdt2.12003

Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu

{"title":"Fragmented software-based self-test technique for online intermittent fault detection in processors","authors":"Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu","doi":"10.1049/cdt2.12003","DOIUrl":"10.1049/cdt2.12003","url":null,"abstract":"<p>Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBST scheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89737149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Efficient design of 15:4 counter using a novel 5:3 counter for high-speed multiplication 高效设计15:4计数器，采用新颖的5:3计数器实现高速乘法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-09 DOI: 10.1049/cdt2.12002

Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S

引用次数: 4

Power efficient error correction coding for on-chip interconnection links 片上互连链路的功率高效纠错编码

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-10-01 DOI: 10.1049/iet-cdt.2019.0082

Sumitra Velayudham, Sivakumar Rajagopal, Yeragudipati Venkata Ramana Rao, Seok-Bum Ko

{"title":"Power efficient error correction coding for on-chip interconnection links","authors":"Sumitra Velayudham, Sivakumar Rajagopal, Yeragudipati Venkata Ramana Rao, Seok-Bum Ko","doi":"10.1049/iet-cdt.2019.0082","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0082","url":null,"abstract":"<div>\u0000 <p>A configurable self-calibrated power efficient five-bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher-order error up to 9 bits with an error correction probability tolerance of 73% for on-chip interconnection links. Single error correction and double error detection with extended Hamming code (22,16) is utilised along with standard triplication error correction methods in the proposed code. Self-calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network-on-chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state-of-the-art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state-of-the-art works. The proposed code is more appropriate for on-chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0082","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72137097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Ten years of hardware Trojans: a survey from the attacker's perspective 硬件木马的十年：从攻击者的角度进行的调查

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-30 DOI: 10.1049/iet-cdt.2020.0041

Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill

{"title":"Ten years of hardware Trojans: a survey from the attacker's perspective","authors":"Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill","doi":"10.1049/iet-cdt.2020.0041","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0041","url":null,"abstract":"<div>\u0000 <p>Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property vendor attacks, computer-aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field-programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti-detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2020.0041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71987479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation 基于同构消去的片上网络启发式映射NoC优化算法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-29 DOI: 10.1049/iet-cdt.2019.0212

Weng Xiaodong, Liu Yi, Yang Yintang

{"title":"Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation","authors":"Weng Xiaodong, Liu Yi, Yang Yintang","doi":"10.1049/iet-cdt.2019.0212","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0212","url":null,"abstract":"<div>\u0000 <p>With the development of network-on-chip (NoC) theory, lots of mapping algorithm have been proposed to solve the application mapping problem which is an NP-hard (non-polynomial hard) problem. Most algorithms are based on a heuristic algorithm. They are trapped by iterations limited, not by the distance between iterations, because of the isomorphism of mapping sequence. In this study, the authors define and analyse the isomorphism with the genetic algorithm (GA) which is a heuristic algorithm. Then, they proposed an approach called density direction transform algorithm to eliminate the isomorphism of mapping sequence and accelerate the convergence of population. To verify this approach, they developed a density-direction-based genetic mapping algorithm (DDGMAP) and make a comparison with genetic mapping algorithm (GMA). The experiment demonstrates that compared to the random algorithm, their algorithm (DDGMAP) can achieve on an average 23.48% delay reduction and 7.15% power reduction. And DDGMAP gets better performance than GA in searching the optimal solution.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0212","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71986614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead 基于加权前瞻的量子电路二维近邻实现技术

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2019.0257

Lalengmawia Chhangte, Alok Chakrabarty

{"title":"Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead","authors":"Lalengmawia Chhangte, Alok Chakrabarty","doi":"10.1049/iet-cdt.2019.0257","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0257","url":null,"abstract":"<div>\u0000 <p>Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubits and the swap gate insertion techniques affect the circuit cost. The authors proposed a global qubit ordering technique that considers fewer permutations for the number of interactions a qubit does with other qubits of its circuit. They also performed the local re-ordering of qubits by attempting to reduce the cost as much as possible; the cost is estimated by defining a window with weights assigned in such a way that nearby gates to the current gate in question are given higher weightage. Experiments have been conducted on NCV benchmarks, and results have been compared with those of recent state-of-the-art techniques. When compared with the existing works, the proposed method shows improvements of up to 53.3% for smaller benchmarks and up to 51.61% for larger benchmarks.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0257","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation 基于优化经验模式分解和非局部均值估计的实时语音增强

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2020.0034

Sagar Reddy Vumanthala, Bikshalu Kalagadda

{"title":"Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation","authors":"Sagar Reddy Vumanthala, Bikshalu Kalagadda","doi":"10.1049/iet-cdt.2020.0034","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0034","url":null,"abstract":"<div>\u0000 <p>In this study, the authors present a novel speech enhancement method by exploring the benefits of non-local means (NLM) estimation and optimised empirical mode decomposition (OEMD) adopting cubic-spline interpolation. The optimal parameters responsible for improving the performance are estimated using the path-finder algorithm. At first, the noisy speech signal is decomposed into many scaled signals called intrinsic-mode functions (IMFs) through the use of a temporary decomposition method is called sifting process in OEMD approach. The obtained IMFs are processed by NLM estimation technique in terms of non-local similarities present in each IMF, to reduce the ill-effects caused by interfering noise. The proposed NLM-based method is effective to eliminate the noise of less-frequency. Each IMF contains essential information about the signals, on some scale or frequency band. Field programmable gate array architecture is implemented on a Xilinx ISE 14.5 and the result of the proposed method offers good performance with a high signal-to-noise ratio (SNR) and low mean-square error compared to other approaches. The performance evolution is carried out for different speech signals taken from the TIMIT database and noises taken from the NOISEX-92 database in different SNR stages of 0, 5 and 10 dB, respectively.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2020.0034","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC 用于最小化2D和3D IC串扰的直线布线算法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-09-18 DOI: 10.1049/iet-cdt.2020.0010

Khokan Mondal, Subhajit Das, Tuhina Samanta

{"title":"Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC","authors":"Khokan Mondal, Subhajit Das, Tuhina Samanta","doi":"10.1049/iet-cdt.2020.0010","DOIUrl":"https://doi.org/10.1049/iet-cdt.2020.0010","url":null,"abstract":"<div>\u0000 <p>The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2020-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2020.0010","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71984669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0