IET Computers and Digital Techniques最新文献_第7页

Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors 低功耗快速傅立叶变换硬件架构，结合了分裂基蝴蝶和高效加法器压缩器

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2021-03-11 DOI: 10.1049/cdt2.12015

Guilherme Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. Costa, Sergio Bampi

{"title":"Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors","authors":"Guilherme Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. Costa, Sergio Bampi","doi":"10.1049/cdt2.12015","DOIUrl":"10.1049/cdt2.12015","url":null,"abstract":"Fast Fourier transform (FFT) is the most common low-complexity implementation of the discrete Fourier transform, intensively employed to process real-world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low-power FFT hardware architecture combining split-radix decimation-in-time butterfly and 5-2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65-nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split-radix butterfly is 13.28% more power efficient than the radix-4 one. The results further show that, by combining 5-2 AC within the split-radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state-of-the-art radix-4 butterfly employing the adder automatically selected by the logic synthesis tool.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"230-240"},"PeriodicalIF":1.2,"publicationDate":"2021-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76324659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller 一种新型的基于fpga的扩展卡尔曼滤波器用于恒开关频率异步电动机无速度传感器直接转矩控制

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2021-03-10 DOI: 10.1049/cdt2.12011

Remzi Inan

{"title":"A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller","authors":"Remzi Inan","doi":"10.1049/cdt2.12011","DOIUrl":"10.1049/cdt2.12011","url":null,"abstract":"This study proposes an FPGA-based hardware in the loop (HIL) emulator for speed-sensorless of induction motor (IM) constant switching frequency controller-based direct torque control (CSFC-DTC) with a novel bi input-reduced order extended Kalman filter (BI-ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed-loop speed-sensorless drive system of IM on the Xilinx Virtex XC5VLX-110T ML506 FPGA board. In this HIL emulator of speed-sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI-ROEKF which is proposed for the first time in the literature. The proposed BI-ROEKF is created by applying two different non-linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed-sensorless drive system of IM is implemented on FPGA using the advantage of hand-written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model-based estimator like the novel BI-ROEKF and hence the control performance of drive system. The estimation performance of the novel BI-ROEKF is tested with speed-sensorless CSFC-DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed-sensorless BI-ROEKF-based CSFC-DTC of the IM are presented.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"185-201"},"PeriodicalIF":1.2,"publicationDate":"2021-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12011","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88381546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Low-space bit-serial systolic array architecture for interleaved multiplication over GF(2m) GF(2m)上交错乘法的低空间位串行收缩阵列结构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2021-03-10 DOI: 10.1049/cdt2.12026

Atef Ibrahim

引用次数: 2

Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology 可靠的SRAM使用NAND-NOR门在超越cmos QCA技术

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2021-02-28 DOI: 10.1049/cdt2.12012

Marshal Raj, Lakshminarayanan Gopalakrishnan, Seok-Bum Ko

{"title":"Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology","authors":"Marshal Raj, Lakshminarayanan Gopalakrishnan, Seok-Bum Ko","doi":"10.1049/cdt2.12012","DOIUrl":"10.1049/cdt2.12012","url":null,"abstract":"The rise in complementary metal-oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond-CMOS technologies to stay in race with Moore’s law. Quantum-dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond-CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND-NOR logic. In QCA, the NAND-NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost-efficient NAND-NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND-NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"202-213"},"PeriodicalIF":1.2,"publicationDate":"2021-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12012","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74024452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor 更正:用于椭圆曲线加密处理器的吞吐量/面积优化的流水线架构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2021-01-11 DOI: 10.1049/cdt2.12008

Muhammad Rashid

引用次数: 0

Recycled integrated circuit detection using reliability analysis and machine learning algorithms 回收集成电路检测使用可靠性分析和机器学习算法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-16 DOI: 10.1049/cdt2.12005

Udaya Shankar Santhana Krishnan, Kalpana Palanisamy

{"title":"Recycled integrated circuit detection using reliability analysis and machine learning algorithms","authors":"Udaya Shankar Santhana Krishnan, Kalpana Palanisamy","doi":"10.1049/cdt2.12005","DOIUrl":"10.1049/cdt2.12005","url":null,"abstract":"The use of counterfeit integrated circuits (ICs) in electronic products decreases its quality and lifetime. Recycled ICs can be detected by the method of aging analysis. Aging is carried out through reliability analysis with the effect of hot carrier injection and bias temperature instability (BTI). In this work, three machine learning methods, namely K-means clustering, back propagation neural network (BPNN) and support vector machines (SVMs), are used to detect the recycled IC aged for a shorter period (1 day) with minimum data size. This work also distinguishes the effects of degradation due to process variations and reliability effects. The reliability and Monte Carlo simulation are performed on benchmark circuits such as c17, s27, b02 and fully differential folded-cascode amplifier using the Cadence Virtuoso tool, and the parameters such as minimum voltage, delay value, supply current, gain, phase margin and bandwidth are measured. Machine learning methods are developed using MATLAB to train and classify the parameters. From the results obtained, it is observed that the classification rate for the benchmark circuits is 100%, and using BPNN, K-means clustering and SVM and the proposed method, recycled IC or used IC is detected even if it was used for 1 day.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"20-35"},"PeriodicalIF":1.2,"publicationDate":"2020-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12005","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79014735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip 基于优化骑士遍历技术的多故障检测及模块序列图的微流控生物芯片重构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-16 DOI: 10.1049/cdt2.12004

Basudev Saha, Mukta Majumder

{"title":"An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip","authors":"Basudev Saha, Mukta Majumder","doi":"10.1049/cdt2.12004","DOIUrl":"10.1049/cdt2.12004","url":null,"abstract":"Conventional biomedical analysers are replaced by digital microfluidic biochips and they are adequate to integrate different biomedical functions, essential for diverse bioassay operations. From the last decade, microfluidic biochips are getting plenty of acceptances in the field of miscellaneous healthcare sectors like DNA analysis, drug discovery and clinical diagnosis. These devices are also bearing a vital role in the area of safety critical applications such as food safety testing, air quality monitoring etc. As these devices are used in safety critical applications, clinical diagnosis and real-time biomolecular assay operations, these must have properties like precision, reliability and robustness. To accept it for discriminating purposes, the microfluidic device must endorse its preciseness and strength by following sublime testing strategy. Here, an optimized droplet traversal technique is proposed to investigate the multiple defective electrodes of a digital microfluidic biochip by embedding boundary cum row traversal and KNIGHT traversal procedure (based on the famous Knight Tour Problem). The proposed approach also enumerates the traversal time for a fault-free biochip. In addition to identifying the faulty electrodes, a Module Sequencing Graph based reconfiguration technique is proposed here to reinstate the device for normal bioassay operation.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"1-11"},"PeriodicalIF":1.2,"publicationDate":"2020-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72622469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator 采用面积和功率优化的硬倍频发生器的基数8模2n乘法器

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-13 DOI: 10.1049/cdt2.12001

Naveen Kr. Kabra, Zuber M. Patel

{"title":"A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator","authors":"Naveen Kr. Kabra, Zuber M. Patel","doi":"10.1049/cdt2.12001","DOIUrl":"10.1049/cdt2.12001","url":null,"abstract":"The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix-8 booth-encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉-2 prefix levels and total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit-45 nm technology. The post-synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post-layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post-layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"36-55"},"PeriodicalIF":1.2,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78496049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fragmented software-based self-test technique for online intermittent fault detection in processors 基于碎片化软件的处理器间歇故障在线自检技术

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-13 DOI: 10.1049/cdt2.12003

Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu

{"title":"Fragmented software-based self-test technique for online intermittent fault detection in processors","authors":"Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu","doi":"10.1049/cdt2.12003","DOIUrl":"10.1049/cdt2.12003","url":null,"abstract":"Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBST scheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"56-76"},"PeriodicalIF":1.2,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89737149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Efficient design of 15:4 counter using a novel 5:3 counter for high-speed multiplication 高效设计15:4计数器，采用新颖的5:3计数器实现高速乘法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-12-09 DOI: 10.1049/cdt2.12002

Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S

引用次数: 4