A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller
IF 1.1 4区 计算机科学Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
{"title":"A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller","authors":"Remzi Inan","doi":"10.1049/cdt2.12011","DOIUrl":null,"url":null,"abstract":"<p>This study proposes an FPGA-based hardware in the loop (HIL) emulator for speed-sensorless of induction motor (IM) constant switching frequency controller-based direct torque control (CSFC-DTC) with a novel bi input-reduced order extended Kalman filter (BI-ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed-loop speed-sensorless drive system of IM on the Xilinx Virtex XC5VLX-110T ML506 FPGA board. In this HIL emulator of speed-sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI-ROEKF which is proposed for the first time in the literature. The proposed BI-ROEKF is created by applying two different non-linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed-sensorless drive system of IM is implemented on FPGA using the advantage of hand-written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model-based estimator like the novel BI-ROEKF and hence the control performance of drive system. The estimation performance of the novel BI-ROEKF is tested with speed-sensorless CSFC-DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed-sensorless BI-ROEKF-based CSFC-DTC of the IM are presented.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"185-201"},"PeriodicalIF":1.1000,"publicationDate":"2021-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12011","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12011","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 1
Abstract
This study proposes an FPGA-based hardware in the loop (HIL) emulator for speed-sensorless of induction motor (IM) constant switching frequency controller-based direct torque control (CSFC-DTC) with a novel bi input-reduced order extended Kalman filter (BI-ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed-loop speed-sensorless drive system of IM on the Xilinx Virtex XC5VLX-110T ML506 FPGA board. In this HIL emulator of speed-sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI-ROEKF which is proposed for the first time in the literature. The proposed BI-ROEKF is created by applying two different non-linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed-sensorless drive system of IM is implemented on FPGA using the advantage of hand-written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model-based estimator like the novel BI-ROEKF and hence the control performance of drive system. The estimation performance of the novel BI-ROEKF is tested with speed-sensorless CSFC-DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed-sensorless BI-ROEKF-based CSFC-DTC of the IM are presented.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.