Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
{"title":"高效设计15:4计数器，采用新颖的5:3计数器实现高速乘法","authors":"Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S","doi":"10.1049/cdt2.12002","DOIUrl":null,"url":null,"abstract":"<p>This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re-ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16-bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":null,"pages":null},"PeriodicalIF":1.1000,"publicationDate":"2020-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12002","citationCount":"4","resultStr":"{\"title\":\"Efficient design of 15:4 counter using a novel 5:3 counter for high-speed multiplication\",\"authors\":\"Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S\",\"doi\":\"10.1049/cdt2.12002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re-ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16-bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.</p>\",\"PeriodicalId\":50383,\"journal\":{\"name\":\"IET Computers and Digital Techniques\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.1000,\"publicationDate\":\"2020-12-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12002\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IET Computers and Digital Techniques\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12002\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12002","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Efficient design of 15:4 counter using a novel 5:3 counter for high-speed multiplication
This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re-ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16-bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.
期刊介绍：
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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