IET Computers and Digital Techniques最新文献

{"title":"Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA","authors":"Mangal D. Gupta,&nbsp;Rajeev K. Chauhan","doi":"10.1049/cdt2.12027","DOIUrl":"10.1049/cdt2.12027","url":null,"abstract":"<p>The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short-period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider-based pseudorandom bit generator is compared with other LCG-based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 2^{2<b><i>n</i></b>} pseudorandom bits for <i>n</i>-bit operands size which leads to lowering the hardware cost. Secondly, it generates high-speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex-5, Virtex-7, and Artix-7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look-up-tables and flip-flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"349-361"},"PeriodicalIF":1.2,"publicationDate":"2021-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12027","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85914620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Noise-based logic locking scheme against signal probability skew analysis","authors":"Ahmad Rezaei,&nbsp;Ali Mahani","doi":"10.1049/cdt2.12022","DOIUrl":"10.1049/cdt2.12022","url":null,"abstract":"<p>Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its functionality is retrieved when the right key is loaded onto it. We propose ‘noise-based’ logic locking, consisting of two separate compliment blocks, which function in three states. By flipping a signal once in the circuit, these modules add corruption to the circuit, whereas either flipping the same signal twice or not flipping leads to the correct functionality. Thus, a low probability skew with a low corruption in the output is obtained by utilisation of these flipping states. We have improved SAT attack resiliency based on time by 17% for a locking block with 14 primary inputs in comparison with the well-known anti-SAT. The area overhead is less in comparison with other schemes, in which extra dummy parts or obfuscation elements are added to their circuit. Also, more crucially, our locking blocks are immune to SPS attack solely. After executing various attacks, retrieved circuits indicate improved overall resiliency against automatic test pattern generation based and approximate guided removal attacks as well.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"279-295"},"PeriodicalIF":1.2,"publicationDate":"2021-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12022","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76173626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing the security of memory in cloud infrastructure through in-phase change memory data randomisation","authors":"Xianzhong Zhou,&nbsp;Ying Wang","doi":"10.1049/cdt2.12023","DOIUrl":"10.1049/cdt2.12023","url":null,"abstract":"<p>As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear-out attacks from malicious applications. However, it is also found that the non-volatile nature and the programming behaviour of PCM bring other security challenges to the memory system. The authors examine the potential risk of information leakage and theft in memory management for PCM-based cloud server or multitenant systems. By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in-memory data obfuscation mechanism to defend against memory attacks or information leakage during page reallocation mandated by OS. With the capabilities of in-memory data randomisation, the proposed SecuRAM avoids the long write latency of PCM cells to erase the content, and achieves higher data initialisation efficiency than conventional software solutions. Second, the proposed SecuRAM also provides a novel solution of fast in-memory hardware fingerprinting and random number generation, which are common and essential security functions in encryption or access authentication to protect confidential memory data from attackers. Two novel techniques are proposed to generate signatures and random numbers: the first is based on partial programming, which works in the same way as bulk data randomisation; the second is loop-counting, which is an overhead-free method by reusing the cell programming mechanism in iterate-write PCM devices. Through evaluation, SecuRAM shows a much better performance and energy-efficiency than conventional measures for PCM memory.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"321-334"},"PeriodicalIF":1.2,"publicationDate":"2021-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12023","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80013069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Static power model for CMOS and FPGA circuits","authors":"Anas Razzaq,&nbsp;Andy Ye","doi":"10.1049/cdt2.12021","DOIUrl":"10.1049/cdt2.12021","url":null,"abstract":"<p>In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"263-278"},"PeriodicalIF":1.2,"publicationDate":"2021-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12021","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82337413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling and verification of parameterized architectures: A functional approach","authors":"Salah Merniz,&nbsp;Saad Harous","doi":"10.1049/cdt2.12024","DOIUrl":"10.1049/cdt2.12024","url":null,"abstract":"<p>The merit of higher order functions for hardware description and transformation is widely acknowledged by hardware designers. However, the use of higher order types makes their correctness proof very difficult. Herein, a new proof approach based on the principle of partial application is proposed which transforms higher order functions into partially applied first-order ones. Therefore, parameterised architectures modelled by higher order functions could be easily redefined only over first-order types. The proof could be performed by induction within the same specification framework that avoids translating the higher order properties between different semantics, which remains extremely difficult. Using the notion of parameterisation where verified components are used as parameters to build more complex ones, the approach fits elegantly in the incremental bottom-up design where both the design and its proof could be developed in a systematic way. The potential features of the proposed methodological proof approach are demonstrated over a detailed example of a circuit design and verification within a functional framework.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"335-348"},"PeriodicalIF":1.2,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12024","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80715860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and low-power leading-one detectors for energy-efficient logarithmic computing","authors":"Mohammad Saeed Ansari,&nbsp;Shyama Gandhi,&nbsp;Bruce F. Cockburn,&nbsp;Jie Han","doi":"10.1049/cdt2.12019","DOIUrl":"10.1049/cdt2.12019","url":null,"abstract":"<p>The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the <i>d</i> least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the <i>d</i> LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs <i>N</i> &lt; 2^<i>d</i>. Additionally, a scaling scheme is proposed that scales up the input <i>N</i> &lt; 2^<i>d</i> to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input <i>N</i> to the LOD; the more significant half is passed if there is at least one ‘1’ in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8× more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"241-250"},"PeriodicalIF":1.2,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85907537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based implementation of floating point processing element for the design of efficient FIR filters","authors":"Tintu Mary John,&nbsp;Shanty Chacko","doi":"10.1049/cdt2.12010","DOIUrl":"10.1049/cdt2.12010","url":null,"abstract":"<p>Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross-Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"296-301"},"PeriodicalIF":1.2,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12010","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83302759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New scan compression approach to reduce the test data volume","authors":"Pralhadrao V. Shantagiri,&nbsp;Rohit Kapur,&nbsp;Chandrasekar Shastry","doi":"10.1049/cdt2.12020","DOIUrl":"10.1049/cdt2.12020","url":null,"abstract":"<p>The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip-flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic-0 and logic-1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"251-262"},"PeriodicalIF":1.2,"publicationDate":"2021-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12020","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88164538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel task scheduling approach for dependent non-preemptive tasks using fuzzy logic","authors":"Heba E. Hassan,&nbsp;Gihan Nagib,&nbsp;Khaled Hosny Ibrahiem","doi":"10.1049/cdt2.12018","DOIUrl":"10.1049/cdt2.12018","url":null,"abstract":"<p>Multiprocessor task scheduling problem is a pressing problem that affects systems' performance and is still being investigated by the researchers. Finding the optimal schedules is considered to be a computationally hard problem. Recently, researchers have used fuzzy logic in the field of task scheduling to achieve optimal performance, but this area of research is still not well investigated. In addition, there are various scheduling algorithms that used fuzzy logic but most of them are often performed on uniprocessor systems. This article presents a new proposed algorithm in which the priorities of the tasks are derived from the fuzzy logic and bottom level parameter. This approach is designed to find task schedules with optimal or sub-optimal lengths in order to achieve high performance for a multiprocessor environment. With respect to the proposed algorithm, the precedence constraints between the non-preemptive tasks and their execution times are known and described by a directed acyclic graph. The number of processors is fixed, the communication costs are negligible and the processors are homogeneous. The suggested technique is tested and compared with the Prototype Standard Task Graph Set.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"214-222"},"PeriodicalIF":1.2,"publicationDate":"2021-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12018","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82794869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things","authors":"Bahram Rashidi","doi":"10.1049/cdt2.12025","DOIUrl":"10.1049/cdt2.12025","url":null,"abstract":"&lt;p&gt;The advancements in wireless communication have created exponential growth in the Internet of Things (IoT) systems. Security and privacy of the IoT systems are critical challenges in many data-sensitive applications. Herein, high-throughput and flexible hardware implementations of the Camellia block cipher for IoT applications are presented. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. The proposed structures for Camellia are designed and shared for implementing the encryption process and generating some intermediate key values in the two separate times. The most complex block in these ciphers is the substitution box (S-box). The S-boxes are implemented based on area-optimised logic circuits. The Camellia S-boxes consist of a field inversion over &lt;math&gt;\u0000 &lt;msub&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;F&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msup&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;2&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;8&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msup&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;&lt;/math&gt; and two affine transformations over &lt;math&gt;\u0000 &lt;msub&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;F&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;2&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;&lt;/math&gt;. The inversion operation is implemented over the composite field &lt;math&gt;\u0000 &lt;msub&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;F&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msup&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msup&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;2&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;4&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msup&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;2&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msup&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;&lt;/math&gt; instead of an inversion over &lt;math&gt;\u0000 &lt;msub&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;F&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msup&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;2&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mn&gt;8&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 ","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 3","pages":"171-184"},"PeriodicalIF":1.2,"publicationDate":"2021-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77123108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}