IET Computers and Digital Techniques最新文献_第10页

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips 基于流动的微流控生物芯片测试和诊断的可扩展伪穷举方法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-03-31 DOI: 10.1049/iet-cdt.2018.5029

Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri

引用次数: 1

Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors 基于节点放电器和扭接晶体管的动态CMOS电路性能分析

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-02-10 DOI: 10.1049/iet-cdt.2018.5045

Dhandapani Vaithiyanathan, Ravindra Kumar, Ashima Rai, Khushboo Sharma

{"title":"Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors","authors":"Dhandapani Vaithiyanathan, Ravindra Kumar, Ashima Rai, Khushboo Sharma","doi":"10.1049/iet-cdt.2018.5045","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5045","url":null,"abstract":"<div>\u0000 <p>The incessant growth of devices such as mobile phones, digital cameras, and other portable electronic gadgets has led to a higher amount of research being dedicated to the low power digital and analogue circuits. In this study, a low power-delay-product (PDP) dynamic complementary metal oxide semiconductor (CMOS) circuit design using small swing domino logic with twist-connected transistors is proposed. An improvement in PDP can be achieved by using a node-discharger circuit in the conventional design. The conventional benchmark and modified circuits are implemented in 90 nm CMOS technology with different power supplies, i.e. 1.2, 1, and 0.9 V. Furthermore, a decrease in voltage level for logic ‘1’ and an increase in voltage level for logic ‘0’ is achieved while maintaining the logic threshold accordingly at half of the supply voltage. So, the output voltage swing is reduced and the unnecessary nodes of the pull down network get discharged in pre-charge phase, eventually leading to an improvement when compared with conventional design in overall PDP by 43.21 and 46.83% for two inverted two-input and three-input AND gate dynamic benchmarks, respectively, for a power supply of 1 V.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"107-113"},"PeriodicalIF":1.2,"publicationDate":"2020-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2018.5045","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71950743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches 基于STT RAM的混合缓存中数据块分配和迁移的整数线性规划模型

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-02-10 DOI: 10.1049/iet-cdt.2019.0070

Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei

{"title":"Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches","authors":"Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei","doi":"10.1049/iet-cdt.2019.0070","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0070","url":null,"abstract":"<div>\u0000 <p>Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"97-106"},"PeriodicalIF":1.2,"publicationDate":"2020-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0070","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71950742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Scheme for periodical concurrent fault detection in parallel CRC circuits 并行CRC电路中的周期性并发故障检测方案

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-21 DOI: 10.1049/iet-cdt.2018.5183

Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi

{"title":"Scheme for periodical concurrent fault detection in parallel CRC circuits","authors":"Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi","doi":"10.1049/iet-cdt.2018.5183","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5183","url":null,"abstract":"<div>\u0000 <p>As technology scales down, circuits are more prone to incur in faults and fault detection is necessary to ensure the system reliability. However, fault-detection circuits are also vulnerable to stuck-at faults due to, for example, manufacturing defects or ageing; a fault can cause an incorrect output in the fault-detection scheme; so concurrent fault detection is, therefore, needed. Cyclic redundancy checks (CRCs) are widely used to detect errors in many applications, for example, they are used in communication to detect errors on transmitted frames. In this study, an efficient method to implement concurrent fault detection for parallel CRC computation is proposed. The scheme relies on using a serial CRC computation circuit that is used to periodically check the results obtained from the main module to detect the faults. This introduces a lower circuit overhead than existing schemes. All CRC encoders and decoders that implement the CRC computation in parallel can employ the proposed scheme to detect faults.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"80-85"},"PeriodicalIF":1.2,"publicationDate":"2020-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2018.5183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71972151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Survey on memory management techniques in heterogeneous computing systems 异构计算系统内存管理技术综述

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-21 DOI: 10.1049/iet-cdt.2019.0092

Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman

{"title":"Survey on memory management techniques in heterogeneous computing systems","authors":"Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman","doi":"10.1049/iet-cdt.2019.0092","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0092","url":null,"abstract":"<div>\u0000 <p>A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"47-60"},"PeriodicalIF":1.2,"publicationDate":"2020-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72160107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher 高效灵活的128位CLEFIA分组密码硬件结构

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-09 DOI: 10.1049/iet-cdt.2019.0157

Bahram Rashidi

{"title":"Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher","authors":"Bahram Rashidi","doi":"10.1049/iet-cdt.2019.0157","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0157","url":null,"abstract":"<div>\u0000 <p>In this study, high-throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ( and ). The S-box is implemented based on area-optimised combinational logic circuits. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S-box consists of three steps: a field inversion over and two affine transformations over . The inversion operation is implemented over the composite field instead of inversion over which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"69-79"},"PeriodicalIF":1.2,"publicationDate":"2020-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71948473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Mapping application-specific topology to mesh topology with reconfigurable switches 使用可重新配置的交换机将特定应用拓扑映射到网状拓扑

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-01 DOI: 10.1049/iet-cdt.2018.5202

Pinar Kullu, Yilmaz Ar, Suleyman Tosun, Suat Ozdemir

{"title":"Mapping application-specific topology to mesh topology with reconfigurable switches","authors":"Pinar Kullu, Yilmaz Ar, Suleyman Tosun, Suat Ozdemir","doi":"10.1049/iet-cdt.2018.5202","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5202","url":null,"abstract":"When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors' method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 1","pages":"9-16"},"PeriodicalIF":1.2,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2018.5202","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71936967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Power-efficient reliable register file for aggressive-environment applications 高效可靠的寄存器文件，适用于攻击性环境应用

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-01 DOI: 10.1049/iet-cdt.2018.5047

Ihsen Alouani, Hamzeh Ahangari, Ozcan Ozturk, Smail Niar

{"title":"Power-efficient reliable register file for aggressive-environment applications","authors":"Ihsen Alouani, Hamzeh Ahangari, Ozcan Ozturk, Smail Niar","doi":"10.1049/iet-cdt.2018.5047","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5047","url":null,"abstract":"In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors’ results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 1","pages":"1-8"},"PeriodicalIF":1.2,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2018.5047","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71959306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-objective constraint and hybrid optimisation-based VM migration in a community cloud 社区云中基于多目标约束和混合优化的虚拟机迁移

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-01 DOI: 10.1049/iet-cdt.2018.5243

Pradeepa Parthiban, Pushpalakshmi Raman

{"title":"Multi-objective constraint and hybrid optimisation-based VM migration in a community cloud","authors":"Pradeepa Parthiban, Pushpalakshmi Raman","doi":"10.1049/iet-cdt.2018.5243","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5243","url":null,"abstract":"The growing demand for the cloud community market towards attracting and sustaining the incoming and the available cloud users is addressed actively to meet the competitive environment. There is a good scope for improving the provider capabilities in the cloud in order to satisfy the users with attractive benefits. The study introduces an effective virtual machine (VM) migration strategy using an optimisation algorithm in such a way to facilitate the user selection of the providers based on their budgetary requirements in running their own platforms. The constraints associated with the selection of the provider include cost, revenue, and resource, which are altogether confined as an elective factor. The optimisation algorithm employed for the VM migration is referred to as Taylor series-based salp swarm algorithm (Taylor-SSA) that is the integration of the Taylor series with SSA. The evaluation of the method is progressed using three setups by varying the number of providers and users. The cost, the revenue, and the resource of the proposed method are analysed and concluded that the proposed method acquired a minimal cost, maximal resource gain and revenue.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 1","pages":"37-45"},"PeriodicalIF":1.2,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2018.5243","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71986473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

LFSR generation for high test coverage and low hardware overhead LFSR生成可实现高测试覆盖率和低硬件开销

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-01 DOI: 10.1049/iet-cdt.2019.0042

Leonel Hernández Martínez, Saqib Khursheed, Sudhakar Mannapuram Reddy

{"title":"LFSR generation for high test coverage and low hardware overhead","authors":"Leonel Hernández Martínez, Saqib Khursheed, Sudhakar Mannapuram Reddy","doi":"10.1049/iet-cdt.2019.0042","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0042","url":null,"abstract":"Safety-critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult-to-detect faults with their respective trade-off analysis. This is achieved using Berlekamp-Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline-C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non-concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline-N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non-concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases.","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 1","pages":"27-36"},"PeriodicalIF":1.2,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0042","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71986474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5