IET Computers and Digital Techniques最新文献_第10页

Sensitivity analysis of testability parameters for secure IC design 安全集成电路设计中可测试性参数的灵敏度分析

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-04-17 DOI: 10.1049/iet-cdt.2019.0217

Sreeja Rajendran, Mary Lourde Regeena

{"title":"Sensitivity analysis of testability parameters for secure IC design","authors":"Sreeja Rajendran, Mary Lourde Regeena","doi":"10.1049/iet-cdt.2019.0217","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0217","url":null,"abstract":"<div>\u0000 <p>Insertion of malicious circuits commonly known as Hardware Trojans into an original integrated circuit (IC) design to alter the functionality has been a major concern in recent years. As a result, over the years multiple techniques have been suggested by researchers to combat these malicious threats. Hard to test nets in any logic circuit are the most vulnerable to insertion of Hardware Trojans. Testability analysis is the process of identification of these hard to test nets in a logic circuit. Testability analysis is achieved through the testability metrics namely controllability and observability. Testability metrics can be used as a yardstick in devising efficient Hardware Trojan detection methods. The crux of this study is a novel method for identification of susceptible nets that are prone to Hardware Trojan insertions in a logic circuit. The study also presents a comprehensive analysis of the impact on testability parameters as a result of Hardware Trojans in the identified susceptible nets. The method utilises the testability parameters of nets to define threshold values for isolating susceptible nets in a design. The study details out the impact of the number of trigger inputs as well as the distribution of trigger nets on the testability metrics of digital circuits.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 4","pages":"158-165"},"PeriodicalIF":1.2,"publicationDate":"2020-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0217","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71968645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Amdahl's law in the context of heterogeneous many-core systems – a survey 异质多核心系统背景下的Amdahl定律——综述

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-04-03 DOI: 10.1049/iet-cdt.2018.5220

Mohammed A. Noaman Al-hayanni, Fei Xia, Ashur Rafiev, Alexander Romanovsky, Rishad Shafik, Alex Yakovlev

{"title":"Amdahl's law in the context of heterogeneous many-core systems – a survey","authors":"Mohammed A. Noaman Al-hayanni, Fei Xia, Ashur Rafiev, Alexander Romanovsky, Rishad Shafik, Alex Yakovlev","doi":"10.1049/iet-cdt.2018.5220","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5220","url":null,"abstract":"<div>\u0000 <p>For over 50 years, Amdahl's Law has been the hallmark model for reasoning about performance bounds for homogeneous parallel computing resources. As heterogeneous, many-core parallel resources continue to permeate into the modern server and embedded domains, there has been growing interest in promulgating realistic extensions and assumptions in keeping with newer use cases. This study aims to provide a comprehensive review of the purviews and insights provided by the extensive body of work related to Amdahl's law to date, focusing on computation speedup. The authors show that a significant portion of these studies has looked into analysing the scalability of the model considering both workload and system heterogeneity in real-world applications. The focus has been to improve the definition and semantic power of the two key parameters in the original model: the parallel fraction (<i>f</i>) and the computation capability improvement index (<i>n</i>). More recently, researchers have shown normal-form and multi-fraction extensions that can account for wider ranges of heterogeneity, validated on many-core systems running realistic workloads. Speedup models from Amdahl's law onwards have seen a wide range of uses, such as the optimisation of system execution, and these uses are even more important with the advent of the heterogeneous many-core era.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 4","pages":"133-148"},"PeriodicalIF":1.2,"publicationDate":"2020-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2018.5220","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71927028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

LUT-based high-speed point multiplier for Goldilocks-Curve448 基于LUT的Goldilocks-Curve448高速点乘法器

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-04-03 DOI: 10.1049/iet-cdt.2019.0041

Yasir A. Shah, Khalid Javeed, Muhammad I. Shehzad, Shoaib Azmat

{"title":"LUT-based high-speed point multiplier for Goldilocks-Curve448","authors":"Yasir A. Shah, Khalid Javeed, Muhammad I. Shehzad, Shoaib Azmat","doi":"10.1049/iet-cdt.2019.0041","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0041","url":null,"abstract":"<div>\u0000 <p>Recent studies have shown that existing elliptic curve-based cryptographic standards provide backdoors for manipulation and hence compromise the security. In this regard, two new elliptic curves known as Curve448 and Curve25519 are recently recommended by IETF for transport layer security future generations. Hence, cryptosystems built over these elliptic curves are expected to play a vital role in the near future for secure communications. A high-speed elliptic curve cryptographic processor (ECCP) for the Curve448 is proposed in this study. The area of the ECCP is optimised by performing different modular operations required for the elliptic curve Diffie–Hellman protocol through a unified architecture. The critical path delay of the proposed ECCP is optimised by adopting the redundant-signed-digit technique for arithmetic operations. The segmentation approach is introduced to reduce the required number of clock cycles for the ECCP. The proposed ECCP is developed using look-up-tables (LUTs) only, and hence it can be ported to any field-programmable gate array family or standard ASIC libraries. The authors' ECCP design offers higher speed without any significant area overhead to recent designs reported in the literature.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 4","pages":"149-157"},"PeriodicalIF":1.2,"publicationDate":"2020-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71927029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

The analogy of matchline sensing techniques for content addressable memory (CAM) 内容可寻址存储器（CAM）的匹配线传感技术的相似性

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-04-01 DOI: 10.1049/iet-cdt.2019.0178

Sandeep Mishra, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Anup Dandapat

{"title":"The analogy of matchline sensing techniques for content addressable memory (CAM)","authors":"Sandeep Mishra, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Anup Dandapat","doi":"10.1049/iet-cdt.2019.0178","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0178","url":null,"abstract":"<div>\u0000 <p>Performance of a memory depends on the storage stability, yield and sensing speed. Differential input and the latching time of sense amplifiers are considered as primary performance factors in static random access memory. In a content addressable memory (CAM), the sensing is carried out through the matchline (ML) and the time for evaluation is the key to decide the search speed. The density of CAM is on a rise to accommodate a higher amount of information which increases the power dissipation associated with it. Issues such as the logical threshold variation and lower noise margin between match and mismatch are critical in the operation of a CAM. A good ML sensing technique can reduce the ML power with enhanced evaluation speed. This work provides an analogy of various ML sensing techniques based on their pre-charging, evaluation and performance improvement strategies. Estimation on the power dissipation and evaluation time are made and in-depth analysis on their power-speed-overhead trade-off are carried on 64-bit CAM macros.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"87-96"},"PeriodicalIF":1.2,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0178","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72124999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Single bit-line 11T SRAM cell for low power and improved stability 用于低功耗和提高稳定性的单比特线11T SRAM单元

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-03-31 DOI: 10.1049/iet-cdt.2019.0234

Rohit Lorenzo, Roy Pailly

{"title":"Single bit-line 11T SRAM cell for low power and improved stability","authors":"Rohit Lorenzo, Roy Pailly","doi":"10.1049/iet-cdt.2019.0234","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0234","url":null,"abstract":"<div>\u0000 <p>This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"114-121"},"PeriodicalIF":1.2,"publicationDate":"2020-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71998028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips 基于流动的微流控生物芯片测试和诊断的可扩展伪穷举方法

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-03-31 DOI: 10.1049/iet-cdt.2018.5029

Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri

引用次数: 1

Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors 基于节点放电器和扭接晶体管的动态CMOS电路性能分析

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-02-10 DOI: 10.1049/iet-cdt.2018.5045

Dhandapani Vaithiyanathan, Ravindra Kumar, Ashima Rai, Khushboo Sharma

{"title":"Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors","authors":"Dhandapani Vaithiyanathan, Ravindra Kumar, Ashima Rai, Khushboo Sharma","doi":"10.1049/iet-cdt.2018.5045","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5045","url":null,"abstract":"<div>\u0000 <p>The incessant growth of devices such as mobile phones, digital cameras, and other portable electronic gadgets has led to a higher amount of research being dedicated to the low power digital and analogue circuits. In this study, a low power-delay-product (PDP) dynamic complementary metal oxide semiconductor (CMOS) circuit design using small swing domino logic with twist-connected transistors is proposed. An improvement in PDP can be achieved by using a node-discharger circuit in the conventional design. The conventional benchmark and modified circuits are implemented in 90 nm CMOS technology with different power supplies, i.e. 1.2, 1, and 0.9 V. Furthermore, a decrease in voltage level for logic ‘1’ and an increase in voltage level for logic ‘0’ is achieved while maintaining the logic threshold accordingly at half of the supply voltage. So, the output voltage swing is reduced and the unnecessary nodes of the pull down network get discharged in pre-charge phase, eventually leading to an improvement when compared with conventional design in overall PDP by 43.21 and 46.83% for two inverted two-input and three-input AND gate dynamic benchmarks, respectively, for a power supply of 1 V.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"107-113"},"PeriodicalIF":1.2,"publicationDate":"2020-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2018.5045","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71950743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches 基于STT RAM的混合缓存中数据块分配和迁移的整数线性规划模型

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-02-10 DOI: 10.1049/iet-cdt.2019.0070

Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei

{"title":"Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches","authors":"Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei","doi":"10.1049/iet-cdt.2019.0070","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0070","url":null,"abstract":"<div>\u0000 <p>Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 3","pages":"97-106"},"PeriodicalIF":1.2,"publicationDate":"2020-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cdt.2019.0070","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71950742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Scheme for periodical concurrent fault detection in parallel CRC circuits 并行CRC电路中的周期性并发故障检测方案

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-21 DOI: 10.1049/iet-cdt.2018.5183

Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi

{"title":"Scheme for periodical concurrent fault detection in parallel CRC circuits","authors":"Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi","doi":"10.1049/iet-cdt.2018.5183","DOIUrl":"https://doi.org/10.1049/iet-cdt.2018.5183","url":null,"abstract":"<div>\u0000 <p>As technology scales down, circuits are more prone to incur in faults and fault detection is necessary to ensure the system reliability. However, fault-detection circuits are also vulnerable to stuck-at faults due to, for example, manufacturing defects or ageing; a fault can cause an incorrect output in the fault-detection scheme; so concurrent fault detection is, therefore, needed. Cyclic redundancy checks (CRCs) are widely used to detect errors in many applications, for example, they are used in communication to detect errors on transmitted frames. In this study, an efficient method to implement concurrent fault detection for parallel CRC computation is proposed. The scheme relies on using a serial CRC computation circuit that is used to periodically check the results obtained from the main module to detect the faults. This introduces a lower circuit overhead than existing schemes. All CRC encoders and decoders that implement the CRC computation in parallel can employ the proposed scheme to detect faults.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"80-85"},"PeriodicalIF":1.2,"publicationDate":"2020-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2018.5183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71972151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Survey on memory management techniques in heterogeneous computing systems 异构计算系统内存管理技术综述

IF 1.2 4区计算机科学

IET Computers and Digital Techniques Pub Date : 2020-01-21 DOI: 10.1049/iet-cdt.2019.0092

Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman

{"title":"Survey on memory management techniques in heterogeneous computing systems","authors":"Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman","doi":"10.1049/iet-cdt.2019.0092","DOIUrl":"https://doi.org/10.1049/iet-cdt.2019.0092","url":null,"abstract":"<div>\u0000 <p>A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"47-60"},"PeriodicalIF":1.2,"publicationDate":"2020-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72160107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11