Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2020-03-31 DOI:10.1049/iet-cdt.2018.5029

Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri

引用次数: 1

Abstract

Microfluidics is an upcoming field of science that is going to be used widely in many safety-critical applications including healthcare, medical research and defence. Hence, technologies for fault testing and fault diagnosis of these chips are of extreme importance. In this study, the authors propose a scalable pseudo-exhaustive testing and diagnosis methodology for flow-based microfluidic biochips. The proposed approach employs a divide-and-conquer based technique wherein, large architectures are split into smaller sub-architectures and each of these are tested and diagnosed independently.

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基于流动的微流控生物芯片测试和诊断的可扩展伪穷举方法

微流体是一个即将到来的科学领域，将被广泛用于许多安全关键应用，包括医疗保健、医学研究和国防。因此，这些芯片的故障测试和故障诊断技术具有极其重要的意义。在这项研究中，作者提出了一种可扩展的基于流动的微流控生物芯片的伪穷举测试和诊断方法。所提出的方法采用了一种基于分而治之的技术，其中，将大型体系结构拆分为较小的子体系结构，并对每个子体系结构进行独立的测试和诊断。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.