基于LUT的Goldilocks-Curve448高速点乘法器

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yasir A. Shah, Khalid Javeed, Muhammad I. Shehzad, Shoaib Azmat
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引用次数: 4

摘要

最近的研究表明,现有的基于椭圆曲线的密码标准为操作提供了后门,从而损害了安全性。在这方面,IETF最近推荐了两种新的椭圆曲线Curve448和Curve25519,用于未来几代的传输层安全。因此,建立在这些椭圆曲线上的密码系统有望在不久的将来在安全通信中发挥至关重要的作用。本文提出了一种用于Curve448的高速椭圆曲线密码处理器(ECCP)。ECCP的区域通过统一架构执行椭圆曲线Diffie–Hellman协议所需的不同模块化操作来优化。通过采用冗余带符号数字技术进行算术运算,优化了所提出的ECCP的关键路径延迟。引入分段方法以减少ECCP所需的时钟周期数。所提出的ECCP仅使用查找表(LUT)开发,因此它可以移植到任何现场可编程门阵列系列或标准ASIC库。与文献中报道的最近的设计相比,作者的ECCP设计提供了更高的速度,而没有任何显著的面积开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

LUT-based high-speed point multiplier for Goldilocks-Curve448

LUT-based high-speed point multiplier for Goldilocks-Curve448

Recent studies have shown that existing elliptic curve-based cryptographic standards provide backdoors for manipulation and hence compromise the security. In this regard, two new elliptic curves known as Curve448 and Curve25519 are recently recommended by IETF for transport layer security future generations. Hence, cryptosystems built over these elliptic curves are expected to play a vital role in the near future for secure communications. A high-speed elliptic curve cryptographic processor (ECCP) for the Curve448 is proposed in this study. The area of the ECCP is optimised by performing different modular operations required for the elliptic curve Diffie–Hellman protocol through a unified architecture. The critical path delay of the proposed ECCP is optimised by adopting the redundant-signed-digit technique for arithmetic operations. The segmentation approach is introduced to reduce the required number of clock cycles for the ECCP. The proposed ECCP is developed using look-up-tables (LUTs) only, and hence it can be ported to any field-programmable gate array family or standard ASIC libraries. The authors' ECCP design offers higher speed without any significant area overhead to recent designs reported in the literature.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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