并行CRC电路中的周期性并发故障检测方案

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi
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引用次数: 1

摘要

随着技术规模的缩小,电路更容易发生故障,故障检测是确保系统可靠性的必要条件。然而,由于制造缺陷或老化等原因,故障检测电路也容易出现卡在故障上;故障可能导致故障检测方案中的错误输出;因此,需要同时进行故障检测。循环冗余校验(CRC)在许多应用中被广泛用于检测错误,例如,它们在通信中用于检测传输帧上的错误。在这项研究中,提出了一种有效的方法来实现并行CRC计算的并发故障检测。该方案依赖于使用串行CRC计算电路,该电路用于定期检查从主模块获得的结果以检测故障。这引入了比现有方案更低的电路开销。所有并行实现CRC计算的CRC编码器和解码器都可以使用所提出的方案来检测故障。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Scheme for periodical concurrent fault detection in parallel CRC circuits

Scheme for periodical concurrent fault detection in parallel CRC circuits

As technology scales down, circuits are more prone to incur in faults and fault detection is necessary to ensure the system reliability. However, fault-detection circuits are also vulnerable to stuck-at faults due to, for example, manufacturing defects or ageing; a fault can cause an incorrect output in the fault-detection scheme; so concurrent fault detection is, therefore, needed. Cyclic redundancy checks (CRCs) are widely used to detect errors in many applications, for example, they are used in communication to detect errors on transmitted frames. In this study, an efficient method to implement concurrent fault detection for parallel CRC computation is proposed. The scheme relies on using a serial CRC computation circuit that is used to periodically check the results obtained from the main module to detect the faults. This introduces a lower circuit overhead than existing schemes. All CRC encoders and decoders that implement the CRC computation in parallel can employ the proposed scheme to detect faults.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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