IET Computers and Digital Techniques最新文献

{"title":"An embedded intelligence engine for driver drowsiness detection","authors":"Shirisha Vadlamudi,&nbsp;Ali Ahmadinia","doi":"10.1049/cdt2.12036","DOIUrl":"10.1049/cdt2.12036","url":null,"abstract":"<p>Motor vehicle crashes involving drowsy driving are huge in number all over the world. Many studies revealed that 10%–30% of crashes are due to drowsy driving. Fatigue has costly effects on the safety, health, and quality of life. This drowsiness of drivers can be detected using various methods, for example, algorithms based on behavioural gestures, physiological signals and vitals. Also, few of them are vehicle based. Drowsiness of drivers was detected based on steering wheel movement and lane change patterns. A pattern is derived based on slow drifting and fast corrective steering movement. A prototype that detects the drowsiness of an automobile driver using artificial intelligence techniques, precisely using open-source tools like TensorFlow Lite on a Raspberry Pi development board, is developed. The TensorFlow model is trained on images captured from the video with the help of object detection using cascade classifier. In order to have a better accuracy, an Inception v3 architecture is used in pre-training the model with the image dataset. The final model is created and trained using long short-term memory and then the final TensorFlow model is converted to TensorFlow Lite model and this Lite model is used on Raspberry Pi board to detect the drowsiness of drivers. The results are comparable with desktop-based results in the literature.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 1","pages":"10-18"},"PeriodicalIF":1.2,"publicationDate":"2021-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12036","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78213695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Who is wearing me? TinyDL-based user recognition in constrained personal devices","authors":"Ramon Sanchez-Iborra,&nbsp;Antonio Skarmeta","doi":"10.1049/cdt2.12035","DOIUrl":"10.1049/cdt2.12035","url":null,"abstract":"<p>Deep learning (DL) techniques have been extensively studied to improve their precision and scalability in a vast range of applications. Recently, a new milestone has been reached driven by the emergence of the TinyDL paradigm, which enables adaptation of complex DL models generated by well-known libraries to the restrictions of constrained microcontroller-based devices. In this work, a comprehensive discussion is provided regarding this novel ecosystem, by identifying the benefits that it will bring to the wearable industry and analysing different TinyDL initiatives promoted by tech giants. The specific use case of automatic user recognition from data captured by a wearable device is also presented. The whole development process by which different DL configurations have been embedded in a real microcontroller unit is described. The attained results in terms of accuracy and resource usage confirm the validity of the proposal, which allows precise predictions in a highly constrained platform with limited input information. Therefore, this work provides insights into the viability of the integration of TinyDL models within wearables, which may be valuable for researchers, practitioners, and makers related to this industry.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 1","pages":"1-9"},"PeriodicalIF":1.2,"publicationDate":"2021-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12035","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74789266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture","authors":"Xiaoying Huang,&nbsp;Zhichuan Guo,&nbsp;Mangu Song,&nbsp;Xuewen Zeng","doi":"10.1049/cdt2.12034","DOIUrl":"10.1049/cdt2.12034","url":null,"abstract":"<p>SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high-speed applications. This study proposes a CPU-FPGA co-designed architecture which offloads the SM3 function on field-programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115-flva1517-2-e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU-FPGA-coupled environment.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 6","pages":"427-436"},"PeriodicalIF":1.2,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12034","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80352999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EmRep: Energy management relying on state-of-charge extrema prediction","authors":"Lars Hanschke,&nbsp;Christian Renner","doi":"10.1049/cdt2.12033","DOIUrl":"10.1049/cdt2.12033","url":null,"abstract":"<p>The persistent rise of Energy Harvesting Wireless Sensor Networks entails increasing demands on the efficiency and configurability of energy management. New applications often profit from or even require user-defined time-varying utilities, for example, the health assessment of bridges is only possible at rushhour. However, monitoring times do not necessarily overlap with energy harvest periods. This misalignment is often corrected by over-provisioning the energy storage. Favourable small-footprint and cheap energy storage, however, fill up quickly and waste surplus energy. Hence, EmRep is presented, which decouples the energy management of high-intake from low-intake harvest periods. Based on the State-of-Charge extrema prediction, the authors enhance energy management and reduce saturation of energy storage by design. Considering multiple user-defined utility profiles, the benefits of EmRep in combination with a variety of prediction algorithms, time resolutions, and energy storage sizes are showcased. EmRep is tailored to platforms with small energy storage, in which it is found that it doubles effective utility, and also increases performance by <math>\u0000 <mn>10</mn>\u0000 <mi>%</mi></math> with large-sized storage.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 4","pages":"91-105"},"PeriodicalIF":1.2,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12033","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85793765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Introducing KeyRing self-timed microarchitecture and timing-driven design flow","authors":"Mickael Fiorentino,&nbsp;Claude Thibeault,&nbsp;Yvon Savaria","doi":"10.1049/cdt2.12032","DOIUrl":"10.1049/cdt2.12032","url":null,"abstract":"<p>A self-timed microarchitecture called <i>KeyRing</i> is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 6","pages":"409-426"},"PeriodicalIF":1.2,"publicationDate":"2021-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12032","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90116704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of the Soft Error Assessment Consistency of a JIT-based Virtual Platform Simulator","authors":"","doi":"10.1049/cdt2.12030","DOIUrl":"https://doi.org/10.1049/cdt2.12030","url":null,"abstract":"","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"393"},"PeriodicalIF":1.2,"publicationDate":"2021-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12030","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"137549770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strengthened 32-bit AES implementation: Architectural error correction configuration with a new voting scheme","authors":"Saeideh Sheikhpur,&nbsp;Mahdi Taheri,&nbsp;Mohammad Saeed Ansari,&nbsp;Ali Mahani","doi":"10.1049/cdt2.12031","DOIUrl":"10.1049/cdt2.12031","url":null,"abstract":"<p>Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROM-based S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 6","pages":"395-408"},"PeriodicalIF":1.2,"publicationDate":"2021-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12031","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72733828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SD-SHO: Security-dominated finite state machine state assignment technique with a satisfactory level of hardware optimization","authors":"Nitish Das,&nbsp;Aruna Priya Panchanathan","doi":"10.1049/cdt2.12029","DOIUrl":"10.1049/cdt2.12029","url":null,"abstract":"<p>Recently, the finite state machine (FSM)-based digital controllers are susceptible to fault-injection and side-channel attacks, which makes FSM security a more prominent factor. FSM optimality is another crucial element when designed. A state encoding approach is applied for FSM security and optimization. This article proposes the security-dominated FSM state assignment technique (SD-SHO), which obtains a satisfactory level of FSM optimization as well. It is a deterministic algorithm and consists of two key techniques, such as state assignment using an improved quadratic sum code, and state assignment using a gradient-based interior point method. A fuzzy bi-level programming logic is introduced in the proposed approach for regulating the constituting algorithms optimally. Experiments are conducted to evaluate the FSM security and optimality using the MCNC FSM benchmarks. Results indicate a substantial reduction in the error masking probability using SD-SHO. It also demonstrates that SD-SHO achieves a satisfactory level of area and power reduction compared with other existing works.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"372-392"},"PeriodicalIF":1.2,"publicationDate":"2021-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12029","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82415061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic diagnosis of single fault in interconnect testing of SRAM-based FPGA","authors":"T. Nirmalraj,&nbsp;S. Radhakrishnan,&nbsp;S.K. Pandiyan","doi":"10.1049/cdt2.12028","DOIUrl":"10.1049/cdt2.12028","url":null,"abstract":"<p>Fault detection and diagnosis of a Field-Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck-at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair-wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS’89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is <math>\u0000 <mrow>\u0000 <msub>\u0000 <mrow>\u0000 <mi>log</mi>\u0000 </mrow>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <mrow>\u0000 <mo>(</mo>\u0000 <mfrac>\u0000 <mrow>\u0000 <mi>n</mi>\u0000 <mrow>\u0000 <mo>(</mo>\u0000 <mrow>\u0000 <mi>n</mi>\u0000 <mo>−</mo>\u0000 <mn>1</mn>\u0000 </mrow>\u0000 <mo>)</mo>\u0000 </mrow>\u0000 </mrow>\u0000 <mn>2</mn>\u0000 </mfrac>\u0000 <mo>)</mo>\u0000 </mrow>\u0000 <mo>+</mo>\u0000 <mn>3</mn>\u0000 </mrow></math> where <i>n</i> is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by <math>\u0000 <mrow>\u0000 <msub>\u0000 <mrow>\u0000 <mi>log</mi>\u0000 </mrow>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <mrow>\u0000 <mo>(</mo>\u0000 <mi>n</mi>\u0000 <mo>+</mo>\u0000 <mn>2</mn>\u0000 <mo>)</mo>\u0000 </mrow>\u0000 </mrow></math> when compared with previously published methods available in the literature.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 5","pages":"362-371"},"PeriodicalIF":1.2,"publicationDate":"2021-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12028","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86920312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Homeland security video surveillance system utilising the internet of video things for smart cities","authors":"Yasser Ismail,&nbsp;Mohamed Hammad,&nbsp;Mahmoud Darwich,&nbsp;Wael Elmedany","doi":"10.1049/cdt2.12014","DOIUrl":"10.1049/cdt2.12014","url":null,"abstract":"<p>In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non-standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co-processor that can be used for video surveillance cameras in homeland security. The proposed ME co-processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co-processor is suited for high-efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block-based motion estimation (FSBB-ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB-ME algorithm. Modelism-version10.4a has been used for simulation and time verification testing proposes. The proposed ME co-processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"302-319"},"PeriodicalIF":1.2,"publicationDate":"2021-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73805198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}