Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2021-09-16 DOI:10.1049/cdt2.12034

Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng

引用次数: 2

Abstract

SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high-speed applications. This study proposes a CPU-FPGA co-designed architecture which offloads the SM3 function on field-programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115-flva1517-2-e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU-FPGA-coupled environment.

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采用CPU-FPGA协同设计架构加速SM3哈希算法

中国政府开发的SM3哈希算法应用于信息安全的各个领域，并在商业安全产品中得到广泛应用。然而，软件架构上的实现性能对于高速应用来说是不够的。本研究提出了一种CPU-FPGA协同设计架构，该架构可以卸载现场可编程门阵列上的SM3功能，从而实现高吞吐量。该架构可以使用16个或更多并发流执行SM3散列算法，这意味着可以并行处理多个数据流。本设计在Xilinx XCKU115-flva1517-2-e器件和Dell商用服务器上实现，当并行处理16个独立SM3模块时，本设计的吞吐量可达35.5 Gbps。该架构在cpu - fpga耦合环境下具有优异的性能。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.