{"title":"基于碎片化软件的处理器间歇故障在线自检技术","authors":"Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu","doi":"10.1049/cdt2.12003","DOIUrl":null,"url":null,"abstract":"<p>Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBST scheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"56-76"},"PeriodicalIF":1.1000,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12003","citationCount":"1","resultStr":"{\"title\":\"Fragmented software-based self-test technique for online intermittent fault detection in processors\",\"authors\":\"Vasudevan Matampu Suryasarman, Santosh Biswas, Aryabartta Sahu\",\"doi\":\"10.1049/cdt2.12003\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBST scheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.</p>\",\"PeriodicalId\":50383,\"journal\":{\"name\":\"IET Computers and Digital Techniques\",\"volume\":\"15 1\",\"pages\":\"56-76\"},\"PeriodicalIF\":1.1000,\"publicationDate\":\"2020-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12003\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IET Computers and Digital Techniques\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12003\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12003","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Fragmented software-based self-test technique for online intermittent fault detection in processors
Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBST scheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.
期刊介绍：
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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