Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Marshal Raj, Lakshminarayanan Gopalakrishnan, Seok-Bum Ko
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引用次数: 2

Abstract

The rise in complementary metal-oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond-CMOS technologies to stay in race with Moore’s law. Quantum-dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond-CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND-NOR logic. In QCA, the NAND-NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost-efficient NAND-NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND-NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.

Abstract Image

可靠的SRAM使用NAND-NOR门在超越cmos QCA技术
互补金属氧化物半导体(CMOS)限制的增加促使业界将重点转向CMOS以外的技术,以保持与摩尔定律的竞争。量子点元胞自动机(QCA)被认为是新兴的超cmos技术中的一个突出范例。由于QCA是一项新兴技术,没有适当的布局工具,因此可以通过使用NAND-NOR逻辑实现电路来实现硬件描述语言(HDL)的布局生成。在QCA中,NAND-NOR逻辑通过组合多数门和逆变器或使用一些专用结构来实现。效应半径(RoE)是一个关键因素,它取决于所使用材料的介电常数,它对柱相互作用、极化和扭结能量有影响。较低的影响半径值将对电路的性能产生影响。本文提出了一种低成本的单旋转单元(SRC)逆变器NAND-NOR门,可以在较小的影响半径下工作。利用所提出的门,实现了多路复用器、解码器和创新的存储单元。为了演示使用NAND-NOR逻辑和所提出的模块实现更大电路的能力,实现了一个16*16 SRAM。使用qcaddesigner对提出的设计进行仿真和验证。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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