IEEE Transactions on Nanotechnology最新文献_第4页

Bridging TCAD and AI: A Machine Learning Approach for BioTFET Behavior Prediction 连接TCAD和人工智能：生物晶体管行为预测的机器学习方法

IF 2.5 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-08-06 DOI: 10.1109/TNANO.2026.3720723

Iman Chahardah Cherik;Subir Kumar Maity;Saeed Mohammadi

{"title":"Bridging TCAD and AI: A Machine Learning Approach for BioTFET Behavior Prediction","authors":"Iman Chahardah Cherik;Subir Kumar Maity;Saeed Mohammadi","doi":"10.1109/TNANO.2026.3720723","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3720723","url":null,"abstract":"Predicting the performance of biological tunneling field-effect transistor (Bio-TFET) sensors typically requires computationally intensive and time-consuming Technology Computer-Aided Design (TCAD) simulations. This study proposes an alternative approach—a hybrid Technology Computer-Aided Design–machine learning (TCAD–ML) framework that accelerates and enhances performance prediction for a novel dual-source vertical charge plasma-based BioTFET (DSVCP-TFET). This device uses a Si/SiO2 material system in a vertical setup and a charge plasma technique. For the machine learning side, we designed a fully connected artificial neural network (ANN) with a 32-32-16-8-1 structure. They trained it using TCAD-generated current-voltage data for four different biomolecules: air (k = 1), Urease (k = 1.64), Ferro-cytochrome c (k = 4.7), and Gelatin (k = 12). The trained model demonstrates excellent predictive accuracy, with R² values consistently exceeding 0.997 across all datasets. When it comes to drain current sensitivity for Gelatin, the ML model predicted 1.27 × 105, which matches up well with the TCAD result of 1.79 × 105. This strong agreement further validates the effectiveness of the hybrid framework. The ML model also successfully mirrors the selectivity metrics for different biomolecule pairs. Furthermore, this TCAD–ML method shows that data-driven strategies aren't just a shortcut—they offer a fast, powerful option compared to sticking with pure simulation.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"280-286"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148781512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RAPID: Re-Configurable Adder Tree Based Performance-Incentivized AI Digital CIM Macro 基于性能激励的AI数字CIM宏的可重构加法器树

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-04-01 DOI: 10.1109/TNANO.2026.3680063

Akash Sankhe;Mukul Lokhande;Narendra Singh Dhakad;Radheshyam Sharma;Santosh Kumar Vishvakarma

引用次数: 0

Near-Infrared Photodetector Based on Single-Walled Carbon Nanotubes/Graphene/Al2O3/InGaAs Structure 基于单壁碳纳米管/石墨烯/Al2O3/InGaAs结构的近红外探测器

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-03-24 DOI: 10.1109/TNANO.2026.3677120

Danyang Zhang;Hao Gu;Jun Chen

引用次数: 0

Area and Energy Efficient Carry Select Adder Utilizing Molecular Memristor 利用分子忆阻器的面积和能量高效进位选择加法器

IF 2.5 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-03-29 DOI: 10.1109/TNANO.2026.3698773

Arjuman Ara Mimi;Su-in Yi

{"title":"Area and Energy Efficient Carry Select Adder Utilizing Molecular Memristor","authors":"Arjuman Ara Mimi;Su-in Yi","doi":"10.1109/TNANO.2026.3698773","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3698773","url":null,"abstract":"In-memory computing represents the next phase of digital computation, designed to overcome the von Neumann bottleneck in Big Data applications. However, its effectiveness is limited by the need for advanced materials and architectures to address issues like excessive footprint and multiple serial computation steps. The utilization of molecular switching elements exhibiting multiple deterministic, non-monotonic transitions enables a significant reduction in both device count and computational steps within in-memory computing architectures. This paper presents a new, low-latency architecture for a Molecular Carry Select Adder (MCSLA), leveraging molecular memristors to reduce area and energy consumption. Additionally, state-of-the-art techniques such as column partitioning and broadcasting were incorporated to optimize the design for massive parallelism. Our MCSLA is 36% and 43% faster for 64-bit and 128-bit, respectively, over Molecular Ripple Carry Adder (MRCA). Moreover, it achieves 82% latency, 15% area, and 78% energy efficiency over the fastest Imply-based Carry Select Adder (CSLA) design for 64-bit addition. The paper also details the computational steps, number of memristors, and energy calculations for n-bit adders. Functional correctness is validated using MATLAB and circuit-equivalent Python simulations, with robustness to non-idealities evaluated and energy estimated from experimentally reported data in prior literature.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"203-215"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-Bandwidth Coupling Performance Enhancement Using Si3N4-on-SOI Grating Coupler Platform 利用Si3N4-on-SOI光栅耦合器平台提高多带宽耦合性能

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-03-19 DOI: 10.1109/TNANO.2026.3675855

Tarun Sharma;Balveer Painam;Xingyu Liu;Zunyue Zhang;Shunsuke Murai;Kyoungsik Yu;Zhenzhou Cheng

{"title":"Multi-Bandwidth Coupling Performance Enhancement Using Si3N4-on-SOI Grating Coupler Platform","authors":"Tarun Sharma;Balveer Painam;Xingyu Liu;Zunyue Zhang;Shunsuke Murai;Kyoungsik Yu;Zhenzhou Cheng","doi":"10.1109/TNANO.2026.3675855","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3675855","url":null,"abstract":"Grating couplers (GCs) are the backbone of coupling of light from fibre to the photonic chips. In this article, we have designed and simulated a GC on Si3N4-on-SOI platform. The proposed design uses 700 nm thick Si3N4 grating layer as full etch grating filled with air on the 340 nm thick silicon-on-insulator (SOI). The mode phase matching between single mode optical fibre and unidirectional single GC waveguide is investigated here for the four different wavelength bands. The simulated peak coupling efficiency (CE) at four different wavelength bands (near Infrared, C-Band, O-Band, L-Band) is obtained at constant duty cycle (DC) and grating period (GP) with single full etch of 700 nm thick Si3N4 on 340 nm thick SOI platform. The simulated peak CE for different wavelengths (λ) at 810 nm, 1305 nm, 1550 nm, 1583 nm are obtained with Si3N4-on-SOI platform. The proposed GC design simulation shows good fabrication tolerance in terms of GP, DC and angle of incidence. The design is also compared with SOI & Si3N4 platforms where thickness of Si & Si3N4 is 220 nm, 700 nm respectively. The peak CE with SOI & Si3N4 platforms are obtained as −6.19 dB, −7.08 dB.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"107-112"},"PeriodicalIF":2.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact Mathematical Model and Hardware Implementation of Spike-Frequency Adaptation for Low-Power Neuromorphic Computing 低功耗神经形态计算中尖峰频率自适应的紧凑数学模型及硬件实现

IF 2.5 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-07-06 DOI: 10.1109/TNANO.2026.3710331

M. A. Seenivasan;Prabir Saha;Shubhankar Majumdar;Alak Majumder

{"title":"A Compact Mathematical Model and Hardware Implementation of Spike-Frequency Adaptation for Low-Power Neuromorphic Computing","authors":"M. A. Seenivasan;Prabir Saha;Shubhankar Majumdar;Alak Majumder","doi":"10.1109/TNANO.2026.3710331","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3710331","url":null,"abstract":"The ionic currents in biological neurons and the electron transport in MOSFET devices both exhibit nonlinear dynamics, enabling transistors to emulate neuronal spiking behavior. Transistor–capacitor networks form conductive pathways analogous to biological ion channels such as <inline-formula><tex-math>$Na^+$</tex-math></inline-formula>, <inline-formula><tex-math>$K^+$</tex-math></inline-formula>, <inline-formula><tex-math>$Ca^{2+}$</tex-math></inline-formula>, and <inline-formula><tex-math>$Cl^-$</tex-math></inline-formula>, and generate membrane-like voltages and action-potential-like spikes. This paper formulates an interspike interval (ISI) equation inspired by calcium-activated <inline-formula><tex-math>$K^+$</tex-math></inline-formula> channel behavior, in which spike-frequency adaptation (SFA) currents translate adaptation mechanisms into subthreshold, CMOS-compatible circuit primitives, enabling intrinsic firing-rate self-regulation. The gradual increase in ISI metrics, measured from spikes, demonstrates SFA in the proposed neuron model. SPICE-based simulations that validate adaptive behavior, tunable firing-rate, and signal attenuation properties consistent with theoretical predictions. The simulation results show that the neuron consumes an average power of 15.23 nW and has an energy efficiency of 1.687 fJ/spike at a spike firing rate of 34.81 MHz, and 634.2 fJ/spike at a low spike frequency of 67.8 kHz due to adaptation, highlighting the modeling for CMOS neuron implementation. This approach emphasizes biological adaptive temporal dynamics, together with a variability-aware, low-power CMOS realization, suitable for future neuromorphic accelerator hardware.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"266-274"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mitigating NDR for Improved RF Performance in $mathrm{MoS_{2}}$ Ferroelectric Tunnel FET $ mathm {MoS_{2}}$铁电隧道场效应管降低NDR提高射频性能

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-03-19 DOI: 10.1109/TNANO.2026.3675800

Jagritee Talukdar;Bhaskaran Muralidharan

{"title":"Mitigating NDR for Improved RF Performance in $mathrm{MoS_{2}}$ Ferroelectric Tunnel FET","authors":"Jagritee Talukdar;Bhaskaran Muralidharan","doi":"10.1109/TNANO.2026.3675800","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3675800","url":null,"abstract":"The work realized a steep-slope <inline-formula><tex-math>$mathrm{MoS_{2}}$</tex-math></inline-formula> based negative capacitance-tunnel field effect transistor (NC-TMDTFET) through the incorporation of the ferroelectric layer into the gate stack. The proposed device sustained a subthreshold slope of 0.023 V/decade and 0.018 V/decade in forward and reverse sweep respectively and an <inline-formula><tex-math>$mathrm{ON/OFF}$</tex-math></inline-formula> current ratio of <inline-formula><tex-math>$10^{12}$</tex-math></inline-formula>. The work investigates the effect of the ferroelectric layer on input and output characteristics. In the subsequent observation, it was noted that as the drain voltage increases, there is a decrease in current, indicating the presence of negative differential resistance (NDR) within the proposed device. However, mitigation of such effect in TMD based NC-TFET has not yet been introduced. Hence, to address the NDR issue hetero-dielectric BOX (H-BOX) is introduced which directly influences the gate-to-drain capacitance of the device. We report a 56.71% reduction in <inline-formula><tex-math>$C_{GD}$</tex-math></inline-formula>, a 15.83% improvement in intrinsic delay, and a corresponding 48.95% improvement in cutoff frequency due to the introduction of H-BOX resulting enhancement in device speed. These improvements demonstrate that H-BOX integration effectively enhances key parameters making it a viable solution for analog applications that require high performance and low power consumption.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"113-118"},"PeriodicalIF":2.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area-Efficient, High-Throughput 2T-2MTJ STT-MRAM Architecture for In-Memory Computing Applications 面向内存计算应用的区域高效、高吞吐量2T-2MTJ STT-MRAM架构

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-04-06 DOI: 10.1109/TNANO.2026.3681441

Mohit Gupta;Ravi S. Siddanath;G Prasad;Karnati Paranjai;Manish Goswami;Kavindra Kandpal

{"title":"An Area-Efficient, High-Throughput 2T-2MTJ STT-MRAM Architecture for In-Memory Computing Applications","authors":"Mohit Gupta;Ravi S. Siddanath;G Prasad;Karnati Paranjai;Manish Goswami;Kavindra Kandpal","doi":"10.1109/TNANO.2026.3681441","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3681441","url":null,"abstract":"This paper presents a novel 2T-2MTJ STT-MRAM bit-cell architecture tailored for In-Memory Computing (IMC) applications, designed to address the limitations of conventional memory architectures. Using 2T-2MTJ bit-cells, our design significantly reduces chip area compared to traditional 8Transistor/10Transistor SRAM bitcell architectures while maintaining high throughput and energy efficiency. A tunable clamp voltage sensing scheme is introduced, enabling parallelism and efficient execution of key bitwise operations such as XNOR, NOR, and NAND without the added complexity of Analog-to-Digital Converters (ADC). Benchmarking using NeuroSim with the VGG-8 neural network, trained on the CIFAR-10 dataset, revealed a 208.52% and 95% increase in throughput (measured in TOPS) compared to 10T SRAM and 1T-1MTJ architectures, respectively, along with improvements in chip area, clock frequency, and overall system performance. This work showcases the potential of STT-MRAM-based IMC architectures to enhance energy efficiency, reduce design complexity, and improve scalability for Artificial Intelligence (AI) / Machine Learning (ML) workloads, making it a promising solution for next-generation computing systems.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"151-162"},"PeriodicalIF":2.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147696736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BRAIN-AD: A Bit-Serial, ReRAm-Empowered Digital Processing-In-Memory Macro for Autonomous Driving 脑- ad：用于自动驾驶的位串行、reram授权的内存中数字处理宏

IF 2.5 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-08-04 DOI: 10.1109/TNANO.2026.3720322

Ankit Kumar Tenwar;Mukul Lokhande;Adam Teman;Santosh Kumar Vishvakarma

{"title":"BRAIN-AD: A Bit-Serial, ReRAm-Empowered Digital Processing-In-Memory Macro for Autonomous Driving","authors":"Ankit Kumar Tenwar;Mukul Lokhande;Adam Teman;Santosh Kumar Vishvakarma","doi":"10.1109/TNANO.2026.3720322","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3720322","url":null,"abstract":"Conventional processing-in-memory (PIM) architectures suffer from limited efficiency due to transistor-intensive adder trees and analog-to-digital converter (ADC) overhead. This work presents BRAIN-AD, a bit-serial, ReRAM-based digital PIM macro for energy-efficient autonomous driving assistance systems (ADAS). The proposed design integrates a compact 1-bit multiply-accumulate (MAC) unit combining a 3T1R Re-XNOR non-volatile bit-cell for in-memory multiplication with an area-efficient 10 T pass-transistor full adder for sequential accumulation. A 16 Kb (128 × 128) macro employs sparsity-aware power gating and supports scalable fixed-point computation from 1 to 16 bits via bit-serial execution. Post-layout simulations in 65 nm CMOS achieve peak throughput of 0.72 TOPS and 112 TOPS/W energy efficiency, providing approximately 1.8× higher throughput and 1.95× higher energy efficiency than state-of-the-art digital PIM designs. System-level evaluation using a quantised INT4 NVIDIA PilotNet model shows less than 2.5% accuracy degradation relative to the FP32 baseline. These results establish BRAIN-AD as a robust, scalable, and practical digital PIM solution for resource-constrained ADAS workloads. This work highlights digital ReRAM-based bit-serial PIM as a scalable and robust alternative to analog CIM for safety-critical edge-AI applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"287-294"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148781345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RTL-to-Atoms Synthesis of a Machine Learning Accelerator on Atomic-Scale Computers 原子尺度计算机上机器学习加速器的rtl -to-原子合成

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2026-01-01 Epub Date: 2026-04-29 DOI: 10.1109/TNANO.2026.3689032

Samuel S. H. Ng;Marcel Walter;Simon Hofmann;Jan Drewniok;Robert Wille;Konrad Walus

{"title":"RTL-to-Atoms Synthesis of a Machine Learning Accelerator on Atomic-Scale Computers","authors":"Samuel S. H. Ng;Marcel Walter;Simon Hofmann;Jan Drewniok;Robert Wille;Konrad Walus","doi":"10.1109/TNANO.2026.3689032","DOIUrl":"https://doi.org/10.1109/TNANO.2026.3689032","url":null,"abstract":"As complementary metal-oxide-semiconductor (CMOS) scaling slows and artificial intelligence (AI) demand soars, atomic-scale platforms such as quantum-dot logic based on silicon dangling bond (SiDB) offer a promising path toward energy-efficient computation, yet practical design flows from register- transfer level (RTL) specifications to manufacturable layouts remain limited. This work presents an RTL-to-atoms synthesis framework for a quantized matrix multiply unit (MXU) targeting SiDB-based field-coupled nanocomputing (FCN). Building on recent advances in SiDB-aware electronic design automation (EDA), the framework combines a hierarchical, parameterized RTL architecture with platform-optimized arithmetic logic unit (ALU), reducing the synthesized logic core of processing elements by about <inline-formula><tex-math>$bm {15,%}$</tex-math></inline-formula> compared to prior flows. Key improvements were also made to the synthesis workflow to better optimize for SiDB logic and incorporate figure-of-merit awareness, which together ensure that the synthesized layouts achieve favorable area scaling and throughput while balancing operational robustness. Evaluations across multiple bit-widths show substantial footprint reductions for configurations within the tractable range of the latest placement-and-routing algorithms while preserving testbench-validated correctness from RTL to dot-accurate SiDB layouts, thereby establishing a reproducible benchmark for EDA on atomic-scale computing. This represents a significant milestone, bridging manually intensive workflows with scalable, automated methodologies, providing a valuable foundation for future design efforts for SiDB-based accelerators.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"197-202"},"PeriodicalIF":2.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147937501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0