Comprehensive Analysis of TreeFET: A Circuit Perspective

Abstract

In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (I_ON) and switching ratio (I_ON/I_OFF) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (I_OFF). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (H_IB) is a crucial metric for deciding the performance, the impact of H_IB on analog/RF performance is also studied. Although the parasitic capacitance rises with higher H_IB, better RF performance is observed with H_IB of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both H_IB of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (I_SC), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in H_IB. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (f_OSC) is noticed with H_IB of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in H_IB. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.