T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori
{"title":"Transistors With MoS$_{2}$ Subnanometer Channels Embedded in 2D WSe$_{2}$","authors":"T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori","doi":"10.1109/TNANO.2025.3549522","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3549522","url":null,"abstract":"We investigate the exploitation of one of the latest advancements in the processing of the two-dimensional materials (2DMs) lateral heterostructures (LH) for electronic applications, which involves the generation of subnanometer one-dimensional (1D) channels embedded in a 2D crystal. Such study is done through a multiscale approach combining Density Functional Theory (DFT) and quantum transport calculations to propose and evaluate various Field-Effect Transistors (FETs) based on LH incorporating one-dimensional MoS<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> channels within monolayer WSe<inline-formula><tex-math>$_{2}$</tex-math></inline-formula>. We assess the ultimate performance of the transistors by considering different device configurations, lengths and orientations.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"152-156"},"PeriodicalIF":2.1,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Polynomial Formal Verification of a RISC-V Processor","authors":"Lennart Weingarten;Kamalika Datta;Rolf Drechsler","doi":"10.1109/TNANO.2025.3548265","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3548265","url":null,"abstract":"Verification plays a major role in ensuring the functional correctness of any design. In recent years with growing complexity of processor designs, verification has assumed utmost importance. Simulation-based techniques cannot ensure completeness in verification, and in this regard formal methods prove crucial. Although formal methods guarantee completeness it is hard to quantify the exact time and space complexities. Recently some works have demonstrated that it is possible to achieve polynomial space and time complexities for various arithmetic circuits as well as for processors. In this paper we propose a <italic>Binary Decision Diagram</i> (BDD) based <italic>Polynomial Formal Verification</i> (PFV) approach for verifying processors. As a case study, we discuss the PFV for a multi-cycle processor (viz., MicroRV32) with support for combinational and sequential sub-systems. New data structures and code base are utilized to verify all the functional components. Experimental results reveal that the verification can indeed be performed in polynomial time.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"140-151"},"PeriodicalIF":2.1,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Min Kyun Sohn;Sang-Hoon Kim;Seong Hyun Lee;Jeong Woo Park;Dongwoo Suh
{"title":"Effects of 3D Channel Shape on the Performance of Nanoscale Gate-All-Around FETs","authors":"Min Kyun Sohn;Sang-Hoon Kim;Seong Hyun Lee;Jeong Woo Park;Dongwoo Suh","doi":"10.1109/TNANO.2025.3546872","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3546872","url":null,"abstract":"Recent research on transistors has focused on gate-all-around (GAA) structures, which possess better gate controllability than previous fin field-effect transistor (FinFET) structures. The characteristics of these devices have been optimized through different channel shapes. However, the characteristics of GAA-FETs with channels that have the same cross-sectional area warrant further research. In this study, we simulated n-type GAA-FETs using the Global TCAD Solutions simulation tool to analyze the effective characteristics obtained by setting equal cross-sectional areas. The results show that the total on-current exhibited up to 40.5% enhancement based on shape for the same area. Similarly, under the same conditions, the on/off current ratio exhibited a difference of approximately 1.5 times based on the shape. These findings help determine the optimal shape of the GAA channel and predict the performance when physical limitations restrict the channel shape. Furthermore, they contribute to improving the characteristics of GAA-FETs in mass production.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"129-133"},"PeriodicalIF":2.1,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of Temperature, Strain Rate, and Vacancies on the Mechanical Properties of Aluminum-Doped Bilayer Silicene","authors":"Alexandre Melhorance Barboza;Luis César Rodríguez Aliaga;Daiara Fernandes de Faria;Ivan Napoleão Bastos","doi":"10.1109/TNANO.2025.3546749","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3546749","url":null,"abstract":"Silicene, a two-dimensional material with promising potential for future technological applications, has attracted considerable attention over the past decade. Recent research has focused on modifying silicene's electronic and magnetic properties by means of adsorption or substitutional doping. While the magnetic, electronic, and optical properties of doped silicene have been extensively studied, there is a noticeable gap in the literature regarding its mechanical properties. To address this issue, this study explores the mechanical characteristics of bilayer silicene doped with aluminum under various conditions. By employing molecular dynamics simulations, we investigate the influence of aluminum concentration, defects, temperature, and strain rate on the material's mechanical response. The findings reveal a monotonically decreasing strength with Al concentration in both the zigzag and armchair straining directions. Additionally, the material exhibits high sensitivity to defects, with even a small percentage significantly impairing its mechanical properties. Directional dependence is also observed, with the zigzag direction showing greater sensitivity than the armchair. As strain progresses, initial mono-vacancies evolve into more complex defects, hindering predictions of the mechanical response in certain cases. Lastly, strain rate sensitivity is evaluated, yielding values of 0.0485 and 0.0365 for the zigzag and armchair directions, respectively.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"134-139"},"PeriodicalIF":2.1,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic Analysis of the Effect of the Device-to-Device Variability of Real-World Memristors on the Implementation of Uncoupled Memristive Cellular Nonlinear Networks","authors":"Yongmin Wang;Kristoffer Schnieders;Vasileios Ntinas;Alon Ascoli;Felix Cüppers;Susanne Hoffmann-Eifert;Stefan Wiefels;Ronald Tetzlaff;Vikas Rana;Stephan Menzel","doi":"10.1109/TNANO.2025.3545251","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3545251","url":null,"abstract":"Cellular Nonlinear Networks (CNNs) are a well established computing approach in the domain of analog computing, known for massive parallelism and data processing locality that enable efficient hardware implementations. Combining CNN with non-volatile memristive devices holds the promise to overcome technological hurdles, like scalability issues, and high energy consumption, while also introducing richer dynamics into the field of CNN. Memristive devices based on the valence change mechanism (VCM) show great properties, like bipolar switching, tuneable resistance and non-volatility that are essential for the design of memristive CNN (M-CNN). In this study we design and investigate an uncoupled M-CNN cell implementing the EDGE detection task. This is the first paper investigating the resilience of M-CNN against device-to-device variability. To this end the first experimentally acquired Dynamic Route Map (DRM) of the M-CNN cell is employed. The comparison with simulations results allows for investigating the effect of mechanisms in the VCM device on the performance of the cell. The result of the computation is stored in the VCM device despite the unavoidable variability in the electrical behaviors of different device samples. Furthermore, the theoretically predicted richer dynamics of M-CNNs over traditional CNNs is demonstrated. This work provides crucial insights into design considerations of M-CNNs, especially as here first steps towards the comprehensive analysis on the effect of imperfections and variability of the memristor on M-CNN cell are taken.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"121-128"},"PeriodicalIF":2.1,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ti-Doped ZnO Nanowires: A Breakthrough in Non-Volatile Resistive Memory Application","authors":"Amitabha Nath;Madhuri Mishra;Subhananda Chakrabarti","doi":"10.1109/TNANO.2025.3544438","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3544438","url":null,"abstract":"This paper explores the enhanced resistive memory capabilities of titanium (Ti)-doped zinc oxide (ZnO) nanowires (NWs) based devices. Utilizing pulsed laser deposition (PLD), ZnO NWs were fabricated on a ZnO seed film (SF), while Ti films were deposited using an electron beam evaporation technique. Two distinct devices, TZO NWs and ZnO NWs, were created with gold (Au) interdigitated electrodes (IDE). The TZO NWs based device exhibited superior resistive memory performances, showcasing a maximum window of 2.6 V at +10 V and 1.2 V at –10 V, surpassing the ZnO NWs based device. The introduction of Ti doping in ZnO NWs provided additional active sites for charge collection, introducing localized energy levels and enhancing overall device performance. These findings collectively highlight the scalability of the TZO NWs based device for next-generation non-volatile resistive memory (NVRM) applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"115-120"},"PeriodicalIF":2.1,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143594317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ANN-Driven Modeling of Gate-All-Around Transistors Incorporating Complete Current Profiles","authors":"Anant Singhal;Harshit Agarwal","doi":"10.1109/TNANO.2025.3542165","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3542165","url":null,"abstract":"In this article, we present an Artificial Neural Network (ANN)-based compact model that accurately captures the complete current characteristics of gate-all-around transistors, including drain, gate, and substrate currents. Unlike previous models, our approach simplifies the modeling of substrate current by defining a simple conversion function and by utilizing simpler loss functions that account for physical effects such as impact ionization. This accurate representation of substrate current is critical for addressing hot-carrier-induced reliability concerns. The proposed model is extensively validated with calibrated Technology Computer-Aided Design (TCAD) simulations as well as with experimental data from multiple technologies. Additionally, it demonstrates smooth higher-order derivatives in symmetry tests, ensuring its suitability for RF applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"110-114"},"PeriodicalIF":2.1,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation Study on the Impact of Miniaturization in 3 nm Node 3D Junctionless Transistors","authors":"Luca Scognamiglio;Fabrizio Mo;Chiara Elfi Spano;Marco Vacca;Gianluca Piccinini","doi":"10.1109/TNANO.2025.3539457","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3539457","url":null,"abstract":"Junctionless Nanosheet gate-all-around Field Effect Transistor (JL-NSGAAFET) is a promising technology characterized by the absence of any junctions between source-channel-drain. This absence allows to further scale down transistors while limiting short-channel effects. In this article, JL-NSGAAFET is explored as a potential candidate for the next 3 nm technology node through 3D TCAD simulations. First, we propose and simulate, through fabrication process simulations, a fabrication strategy for the JL-NSGAAFET compatible with the current manufacturing technology and based on the inversion mode NSGAAFET fabrication process. The high-k gate dielectric (HfO<sub>2</sub>) and metal-gate technology (TiN) are also adopted in the fabrication process to enhance the electrostatic gate control over the channel for the n-type and p-type transistors. Then, we perform electrical simulations of the device by also including drift-diffusion model and quantum density gradient correction. We characterize the device in terms of electrical performance and compare with the conventional NSGAAFET. Furthermore, to investigate the impact of the device scaling on the unwanted short channel effects, we simulate and analyze the devices while varying the gate length (L<sub>G</sub>) from 20 nm to 12 nm. Our reported simulation results prove that JL-NSGAAFET exhibits near-ideal subthreshold slope, low drain-induced barrier lowering (DIBL) and high on-to-off current ratio (I<sub>ON</sub>/I<sub>OFF</sub>) with superior advantages of greater drive currents and a simpler fabrication process because of the absence of junctions.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"102-109"},"PeriodicalIF":2.1,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2024 Index IEEE Transactions on Nanotechnology Vol. 23","authors":"","doi":"10.1109/TNANO.2025.3537416","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3537416","url":null,"abstract":"","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"822-847"},"PeriodicalIF":2.1,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10869628","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Insights Into Temperature Sensitivity Analysis of Polarity Controlled Charge Plasma Based Tunable Arsenide/Antimonide Tunneling Interfaced Junctionless TFET","authors":"S. Sharma;J. Madan;R. Chaujar","doi":"10.1109/TNANO.2025.3532313","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3532313","url":null,"abstract":"This research delves into the temperature-dependent performance of a novel polarity-controlled charge plasma-based InAs/AlGaSb tunneling interfaced junctionless TFET (H-JLTFET). The device leverages the benefits of both charge plasma and heterojunction engineering to enhance device performance. Comprehensive simulations were conducted to assess the impact of temperature on device characteristics. Results indicate that while the device exhibits promising ON-state current and high-frequency metrics, with a peak <italic>f<sub>T</sub></i> of 417 GHz and an <italic>f</i><sub>max</sub> of 4390 GHz, the subthreshold region is significantly influenced by temperature. The observed increase in OFF-state current and degradation in subthreshold swing highlight the need for careful thermal management and circuit design. Furthermore, the study reveals a moderate impact of temperature on intrinsic delay and a slight increase in ambipolar current. Overall, this work provides valuable insights into the thermal behavior of H-JLTFETs, paving the way for optimized device design and reliable operation in various applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"96-101"},"PeriodicalIF":2.1,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143465613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}