IEEE Transactions on Nanotechnology最新文献

An Intelligent 3D-AFM Scanning Process Based on Online Probe Rotation and Adaptive Speed Strategy 基于在线探针旋转和自适应速度策略的3D-AFM智能扫描过程

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-30 DOI: 10.1109/TNANO.2025.3565847

Huang-Chih Chen;Sheng-An Lee;Ting-An Chou;Li-Chen Fu

{"title":"An Intelligent 3D-AFM Scanning Process Based on Online Probe Rotation and Adaptive Speed Strategy","authors":"Huang-Chih Chen;Sheng-An Lee;Ting-An Chou;Li-Chen Fu","doi":"10.1109/TNANO.2025.3565847","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3565847","url":null,"abstract":"Atomic Force Microscope (AFM) has remained one of the most prominent morphology tools for examining the microscopic world. However, the 3D-AFM has several disadvantages. First, the physical AFM tip occupies space and may sometimes obstruct the scanning process, creating distorted results, especially for vertical sidewalls. Additionally, the traditional AFM scanning scheme results in sparser data density along steep surfaces. In this work, to alleviate distortion, the AFM probe is allowed to rotate. Moreover, the scanning speed along the fast axis in a scan line has to be adaptive according to terrain variation. Therefore, we aim to develop and implement an intelligent AFM scanning process assisted by the proposed probe rotation decision (PRD) and adaptive speed decision (ASD) modules, enabling the AFM probe to achieve online rotation and variable scan speed. Moreover, methods for online coarse compensation and offline fine compensation are also presented to accurately eliminate tip shifts caused by probe rotation. Finally, some comparison results will be provided to demonstrate the effectiveness of the proposed intelligent scanning process.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"264-276"},"PeriodicalIF":2.1,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144100085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FDSOI-Based Reconfigurable FETs: A Ferroelectric Approach 基于fdsoi的可重构场效应管：铁电方法

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-30 DOI: 10.1109/TNANO.2025.3565720

Donghyeok Lee;Suprem R. Das;Jiseok Kwon;Jiwon Chang

引用次数: 0

Stochastic Templates and Noise Dynamics in Memristor Cellular Nonlinear Networks 记忆电阻细胞非线性网络中的随机模板和噪声动力学

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-30 DOI: 10.1109/TNANO.2025.3565887

Dimitrios Prousalis;Vasileios Ntinas;Christoforos Theodorou;Ioannis Messaris;Ahmet Samil Demirkol;Alon Ascoli;Ronald Tetzlaff

{"title":"Stochastic Templates and Noise Dynamics in Memristor Cellular Nonlinear Networks","authors":"Dimitrios Prousalis;Vasileios Ntinas;Christoforos Theodorou;Ioannis Messaris;Ahmet Samil Demirkol;Alon Ascoli;Ronald Tetzlaff","doi":"10.1109/TNANO.2025.3565887","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3565887","url":null,"abstract":"Noise is a pervasive aspect that impacts various systems and environments, from mobile radio channels to biological systems. Within the framework of complex networks, noise poses significant challenges for functionality and performance. In this paper, we investigate the dynamics of a well-known type of locally-coupled computing networks, Memristor Cellular Nonlinear Networks (M-CNNs), in the presence of noise at their interconnection weights, introducing the concept of stochastic weights. In particular, we analyze the effect of noise originating from the synaptic memristors by incorporating both deterministic and stochastic components into synaptic weights, investigating how device-to-device variability and noise affect network performance. Based on the well-established theory of CNNs, we are extending the stability criteria to incorporate synaptic memristor non-idealities and we provide a theoretical framework to analyze their effect on system's performance. In this work, we employ the physics-based Jülich Aachen Resistive Switching Tools (JART) model to study Valence Change Memory (VCM) devices as synapses within our theoretical framework. We investigate the impact of device variability and noise, utilizing statistical properties derived from experimental data reported in the literature. We demonstrate the efficacy of noisy M-CNNs in performing the edge detection task, an example of fundamental image processing applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"282-292"},"PeriodicalIF":2.1,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Room Temperature Negative Differential Resistance in Gate-All-Around Field-Effect Transistors With 1D Active Channels

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-29 DOI: 10.1109/TNANO.2025.3565276

Amit Verma;Reza Nekovei;Daryoush Shiri

引用次数: 0

A Novel Underlay Metal Strip Loaded Doping-Less Heterojunction (GaSb/Si) TFET Biosensor for Autoimmune Disease Detection 一种用于自身免疫性疾病检测的新型衬底金属条负载无掺杂异质结（GaSb/Si） TFET生物传感器

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-17 DOI: 10.1109/TNANO.2025.3561947

Madhulika Verma;Sachin Agrawal

{"title":"A Novel Underlay Metal Strip Loaded Doping-Less Heterojunction (GaSb/Si) TFET Biosensor for Autoimmune Disease Detection","authors":"Madhulika Verma;Sachin Agrawal","doi":"10.1109/TNANO.2025.3561947","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3561947","url":null,"abstract":"In human being autoimmune diseases are caused by the immune system's attack on body tissues. Therefore, advanced diagnostic tools for their early and accurate detection is highly needed. This study introduces a new underlay metal strip loaded doping-less heterojunction (GaSb/Si) TFET biosensor (UMS-DL-HJ-TFETB) device with exceptional sensitivity and performance. Key design features include an underlay metal strip for improved tunnelling and the cavities are on the source region to achieve a peak drain current sensitivity of 6.7 × 10<inline-formula><tex-math>$^{10}$</tex-math></inline-formula> at k = 12 and V<inline-formula><tex-math>$_{gs}$</tex-math></inline-formula> = 0.45 V. With a cut-off frequency of 3.27 × 10<inline-formula><tex-math>$^{8}$</tex-math></inline-formula> Hz and a response time of 496 ps, the proposed biosensor exhibits excellent RF performance. The device performance in detecting DNA charge densities ranging from <inline-formula><tex-math>$pm$</tex-math></inline-formula>1 × 10<inline-formula><tex-math>$^{11}$</tex-math></inline-formula> cm<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula> to <inline-formula><tex-math>$pm$</tex-math></inline-formula>1 × 10<inline-formula><tex-math>$^{12}$</tex-math></inline-formula> cm<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula> has also been studied. In addition, five non-uniform distributions which is caused by the steric hindrance effect have been optimized. A comparative analysis is also done for fair evaluation. The simulation results show that the proposed biosensor addresses the limitations of conventional methods, providing high sensitivity, rapid detection and reliable diagnostic accuracy for autoimmune diseases.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"239-248"},"PeriodicalIF":2.1,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays 基于RRAM阵列的内存计算应用的向量矩阵乘法器架构

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-15 DOI: 10.1109/TNANO.2025.3560912

Bipul Boro;Rushik Parmar;Gaurav Trivedi

{"title":"Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays","authors":"Bipul Boro;Rushik Parmar;Gaurav Trivedi","doi":"10.1109/TNANO.2025.3560912","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3560912","url":null,"abstract":"Artificial Intelligence (AI) has advanced to the stage where modern problems can be transformed into AI problems with computational costs. Increased complexity has exponentially raised computation and inference demands, primarily due to Von Neumann architecture limitations. In-memory computing (IMC) revolutionizes this paradigm by eliminating memory read-write overheads. Notably, the utilization of Resistive Random Access Memory (RRAM) in vector-matrix multiplication (VMM) configurations within IMC architectures has demonstrated substantial performance enhancements. In the proposed work, utilizing Digital-to-Time Converters (DTCs) and Time-to-Digital Converters (TDCs) optimizes hardware resources substantially within in-memory computing (IMC) architectures. Our proposed DTC and TDC blocks exhibit power consumptions of <inline-formula><tex-math>$41 mu text{W}$</tex-math></inline-formula> and <inline-formula><tex-math>$38 mu text{W}$</tex-math></inline-formula> and delays of <inline-formula><tex-math>$896 text{ps}$</tex-math></inline-formula> and <inline-formula><tex-math>$530 text{ps}$</tex-math></inline-formula>. Additionally, we introduce a <inline-formula><tex-math>$4T-1R$</tex-math></inline-formula> structure with Reset Stop Block (RSB) that facilitates 2-bit RRAM reprogramming and entails a latency of <inline-formula><tex-math>$1.07 mu text{s}$</tex-math></inline-formula> and energy/cell of <inline-formula><tex-math>$0.11 text{pJ}$</tex-math></inline-formula>. The overall energy efficiency of Time-Domain VMM (TDVMM) architecture is <inline-formula><tex-math>$866.6 text{Tops/W}$</tex-math></inline-formula>, which is <inline-formula><tex-math>$1.61 times$</tex-math></inline-formula> more efficient than contemporary TDVMMs. Furthermore, our design consistently performs with a cycle-to-cycle variability of 23%, showcasing its tolerance to variations.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"249-259"},"PeriodicalIF":2.1,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Analysis of TreeFET: A Circuit Perspective 树效应的综合分析：电路的视角

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-14 DOI: 10.1109/TNANO.2025.3560672

N. Aruna Kumari;Brajesh Kumar Kaushik

{"title":"Comprehensive Analysis of TreeFET: A Circuit Perspective","authors":"N. Aruna Kumari;Brajesh Kumar Kaushik","doi":"10.1109/TNANO.2025.3560672","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3560672","url":null,"abstract":"In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (<italic>ION) and switching ratio (<italic>ION/<italic>IOFF) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (<italic>IOFF). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (<italic>HIB) is a crucial metric for deciding the performance, the impact of <italic>HIB on analog/RF performance is also studied. Although the parasitic capacitance rises with higher <italic>HIB, better RF performance is observed with <italic>HIB of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both <italic>HIB of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (<italic>ISC), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in <italic>HIB. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (<italic>fOSC) is noticed with <italic>HIB of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in <italic>HIB. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"231-238"},"PeriodicalIF":2.1,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On-chip Non-Blocking 4 × 4 and 8 × 8 Photonic Switches Using MMI-MZI Configuration for Next-Generation Data Center Networks 采用MMI-MZI配置的片上非阻塞4 × 4和8 × 8光子交换机用于下一代数据中心网络

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-04 DOI: 10.1109/TNANO.2025.3558256

Devendra Chack;Gaurav Kumar

{"title":"On-chip Non-Blocking 4 × 4 and 8 × 8 Photonic Switches Using MMI-MZI Configuration for Next-Generation Data Center Networks","authors":"Devendra Chack;Gaurav Kumar","doi":"10.1109/TNANO.2025.3558256","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3558256","url":null,"abstract":"The advancement of future photonic integrated circuits for data center networks relies crucially on the development of highly efficient, low-power, and compact switches. This paper presents the design of non-blocking 4 × 4 and 8 × 8 silicon photonics switches intended using Multimode Interferometer (MMI)-Mach-Zehnder interferometer (MZI) structures. These proposed switches consist of 2 × 2 MMI-MZI switches realized by changing the phase of an optical signal using the thermo-optic effect. At 1550 nm, the proposed 2 × 2 switch exhibits an insertion loss of 0.04 dB and crosstalk of < 39.95 dB. Similarly, the C-band showcases an insertion loss of < 0.06 dB and crosstalk of < −33 dB. To support complex network topologies and enhance network efficiency, a data center network necessitates a higher quantity of port switches. The results show that at 1550 nm, the insertion loss for the 4 × 4 and 8 × 8 switches is 0.47 dB and 1.02 dB, respectively. Furthermore, the insertion loss for the C-band is < 0.50 dB and < 1.5 dB, respectively. The switches exhibit crosstalk of −37.59 dB and −34.67 dB at 1550 nm, respectively. Additionally, they demonstrate crosstalk of < −30 dB for the C-band. This suggests the potential for further scalability in terms of port counts. The switches are designed using the eigenmode expansion method, and the micro heater is designed with a finite element heat transfer solver. These advantages and excellent performance make the device a promising candidate for use in advanced communication systems and photonic integrated circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"216-223"},"PeriodicalIF":2.1,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of the Voltage Ramp Rate Effects on the Programming Characteristics of Bipolar-Type Memristive Devices 电压斜坡率对双极型记忆器件编程特性的影响分析

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-04-02 DOI: 10.1109/TNANO.2025.3556856

E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff

{"title":"Analysis of the Voltage Ramp Rate Effects on the Programming Characteristics of Bipolar-Type Memristive Devices","authors":"E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff","doi":"10.1109/TNANO.2025.3556856","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3556856","url":null,"abstract":"We investigate in this letter the role the voltage ramp rate plays in the conduction and programming characteristics of bipolar-type memristive devices. It is shown that speeding up the writing or erasing process of a memristor is beneficial in terms of energy consumption but has a side cost associated with power dissipation. This happens because of the dynamical aspects of the set and reset transitions which are ultimately dictated by the physics of metal ions and oxygen vacancies migration. It is shown that by adding a constant base voltage to the voltage sweep, shorter programming times can be achieved but no significant impact on the power dissipation-energy consumption relationship is observed. Modeling and simulations are carried out with the aid of the Dynamic Memdiode Model and its implementation in LTspice using the Method of Elementary Solvers. Since the device model parameters and simulation conditions can vary in a wide range, the complete schematics are provided so that the interested readers can test different casuistries by themselves.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"205-208"},"PeriodicalIF":2.1,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947287","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of SRAM in 3-Dimensional Stacked FET With Direct Backside Contact Beyond 1Nm Node 超1Nm节点直接后接触三维堆叠FET SRAM的研制

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-18 DOI: 10.1109/TNANO.2025.3552308

Mingyu Kim;Ilho Myeong;Jaehyun Park;Sungil Park;Deukho Yeon;Daewon Ha;Hyungcheol Shin

引用次数: 0