IEEE Transactions on Nanotechnology最新文献_第2页

Realization of Compact High-Performance EAM Based on Numerical Analysis of ITO, VO2 and Graphene on SiO2 Platform 基于ITO、VO2和石墨烯在SiO2平台上的数值分析实现紧凑型高性能EAM

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-18 DOI: 10.1109/TNANO.2025.3552525

Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar

{"title":"Realization of Compact High-Performance EAM Based on Numerical Analysis of ITO, VO2 and Graphene on SiO2 Platform","authors":"Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar","doi":"10.1109/TNANO.2025.3552525","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552525","url":null,"abstract":"Plasmonic based electro-absorption modulators (EAMs) has paved the way for high-speed photonic integrated circuits (PICs). This paper demonstrates the numerical analysis and the structural design of the EAM using various plasmonic materials, such as vanadium dioxide (VO2), indium-tin-oxide (ITO) and graphene, to modulate signals traveling through the waveguide on an SiO2 platform. It also explores key performance metrics, including the extinction ratio (ER) and the figure-of-merit (FOM), which is related to the device's insertion loss (IL). By optimizing the structural parameters and utilizing the plasmonic materials, the device characteristics, especially the effective-mode-index (EMI), is modified to attain the epsilon-near-zero (ENZ) condition. The ITO-based EAM attains a high ER of 22.24 dB/μm with a FOM of 482.45, while the graphene-ITO based EAM obtains an ER of 20.31 dB/μm and a FOM of 296.06 at 1.55 μm wavelength. Both devices have an energy consumption per bit (Ebit) below 2.20 fJ/bit and modulation frequency (<inline-formula><tex-math>$f$</tex-math></inline-formula>) exceeding 1300 GHz at an IL <inline-formula><tex-math>$< $</tex-math></inline-formula> 0.07 dB/μm. The investigated EAMs hold potential for future-generation PICs.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"178-188"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage 基于可编程电压可调RRAM的多模式可配置物理不可克隆功能

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-18 DOI: 10.1109/TNANO.2025.3552433

Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu

{"title":"A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage","authors":"Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu","doi":"10.1109/TNANO.2025.3552433","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552433","url":null,"abstract":"Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"166-177"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adaptive Separately Constrained Triplet Loss (A-SCTL) for High-Performance Triplet Networks 高性能三元组网络的自适应分离约束三元组损失（A-SCTL）

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-18 DOI: 10.1109/TNANO.2025.3552233

Ziheng Wang;Farzad Niknia;Shanshan Liu;Honglan Jiang;Siting Liu;Pedro Reviriego;Jun Zhou;Fabrizio Lombardi

{"title":"Adaptive Separately Constrained Triplet Loss (A-SCTL) for High-Performance Triplet Networks","authors":"Ziheng Wang;Farzad Niknia;Shanshan Liu;Honglan Jiang;Siting Liu;Pedro Reviriego;Jun Zhou;Fabrizio Lombardi","doi":"10.1109/TNANO.2025.3552233","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552233","url":null,"abstract":"Triplet Networks (TNs) consist of three subchannels and are widely utilized in machine learning applications. The efficacy of TNs is highly dependent on the loss function employed during training. This paper proposes a novel loss function for TNs, referred to as the Adaptive Separately Constrained Triplet Loss (A-SCTL). The unique feature of A-SCTL is the separation of intra-class and inter-class constraints, strictly adhering to the objective of similarity-measuring networks. Its adaptive strategy leverages the dynamics between inter-class and intra-class terms to achieve a balanced convergence; without manually adjusting hyperparameters, it enhances flexibility and facilitates adaptation across various applications. Moreover, A-SCTL mitigates possible false solutions and offers insights into network behavior through the dependency of the two constraint terms. Performance metrics of the loss functions are evaluated in deep metric learning classification and face recognition tasks. Simulations illustrate the evolution of the two loss terms and the adaptive hyperparameter across training epochs; the results demonstrate that TNs utilizing A-SCTL outperform other existing loss functions in accuracy. Additionally, this paper details the hardware implementation of A-SCTL and evaluates its associated overhead. Results show that compared to other losses, the additional hardware overhead required for A-SCTL is negligible (0.008% energy per operation) when considering the entire TN system.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"157-165"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Robust Hardware-Aware Neural Networks for FeFET-Based Accelerators 基于场效应效应加速器的鲁棒硬件感知神经网络

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-18 DOI: 10.1109/TNANO.2025.3553037

Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam

{"title":"Robust Hardware-Aware Neural Networks for FeFET-Based Accelerators","authors":"Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam","doi":"10.1109/TNANO.2025.3553037","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3553037","url":null,"abstract":"Hardware accelerators based on emerging device technologies are gaining traction for inference workloads, but effective methods for their training remain an open area of research. We propose an efficient hardware-aware methodology for training neural networks with ternary weights that are mappable to emerging memory device arrays. We study device-network interactions across a variety of scenarios using simulated and experimentally measured datasets from ferroelectric field-effect transistor (FeFET) devices with varying characteristics. We quantify the impact of device non-idealities on network training by investigating device-level metrics, network-level metrics, loss landscapes, as well as parameter optimization trajectories. We validate our approach by mapping a hardware-aware solution to an emulated system with parameters calibrated to experimental measurements, highlighting several trade-offs. Hardware-aware training results on FeFET-based multi-layer perceptron networks, long short-term memory networks, and deep convolutional networks demonstrate competitive performance at lower overheads compared to existing schemes, indicating architectural and computational scalability. It is found that devices with low variability, non-linearity, and high dynamic range exhibit training characteristics closest to a software baseline. We provide evidence that device non-idealities inject noise during backpropagation, leading to sharper loss landscapes and higher-dimensional optimization trajectories, which make device networks more difficult to train than software counterparts. We also identify optimal operating voltages for investigated devices by utilizing our hardware-aware training and inference methodologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"189-200"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143808879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience 具有老化弹性的低功耗可靠rram可配置RO PUF

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-12 DOI: 10.1109/TNANO.2025.3569071

Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu

{"title":"A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience","authors":"Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu","doi":"10.1109/TNANO.2025.3569071","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3569071","url":null,"abstract":"Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 <inline-formula><tex-math>$mu W$</tex-math></inline-formula> per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from <inline-formula><tex-math>$-50,^{circ }$</tex-math></inline-formula>C to <inline-formula><tex-math>$150,^{circ }$</tex-math></inline-formula>C and <inline-formula><tex-math>$pm$</tex-math></inline-formula>20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"293-306"},"PeriodicalIF":2.1,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transistors With MoS$_{2}$ Subnanometer Channels Embedded in 2D WSe$_{2}$ 在二维WSe$_{2}$中嵌入MoS$_{2}$亚纳米通道的晶体管

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-11 DOI: 10.1109/TNANO.2025.3549522

T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori

引用次数: 0

Polynomial Formal Verification of a RISC-V Processor RISC-V处理器的多项式形式验证

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-05 DOI: 10.1109/TNANO.2025.3548265

Lennart Weingarten;Kamalika Datta;Rolf Drechsler

引用次数: 0

Effects of 3D Channel Shape on the Performance of Nanoscale Gate-All-Around FETs 三维沟道形状对纳米级全栅极场效应晶体管性能的影响

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-03-03 DOI: 10.1109/TNANO.2025.3546872

Min Kyun Sohn;Sang-Hoon Kim;Seong Hyun Lee;Jeong Woo Park;Dongwoo Suh

引用次数: 0

Influence of Temperature, Strain Rate, and Vacancies on the Mechanical Properties of Aluminum-Doped Bilayer Silicene 温度、应变速率和空位对掺铝双层硅烯力学性能的影响

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-02-28 DOI: 10.1109/TNANO.2025.3546749

Alexandre Melhorance Barboza;Luis César Rodríguez Aliaga;Daiara Fernandes de Faria;Ivan Napoleão Bastos

{"title":"Influence of Temperature, Strain Rate, and Vacancies on the Mechanical Properties of Aluminum-Doped Bilayer Silicene","authors":"Alexandre Melhorance Barboza;Luis César Rodríguez Aliaga;Daiara Fernandes de Faria;Ivan Napoleão Bastos","doi":"10.1109/TNANO.2025.3546749","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3546749","url":null,"abstract":"Silicene, a two-dimensional material with promising potential for future technological applications, has attracted considerable attention over the past decade. Recent research has focused on modifying silicene's electronic and magnetic properties by means of adsorption or substitutional doping. While the magnetic, electronic, and optical properties of doped silicene have been extensively studied, there is a noticeable gap in the literature regarding its mechanical properties. To address this issue, this study explores the mechanical characteristics of bilayer silicene doped with aluminum under various conditions. By employing molecular dynamics simulations, we investigate the influence of aluminum concentration, defects, temperature, and strain rate on the material's mechanical response. The findings reveal a monotonically decreasing strength with Al concentration in both the zigzag and armchair straining directions. Additionally, the material exhibits high sensitivity to defects, with even a small percentage significantly impairing its mechanical properties. Directional dependence is also observed, with the zigzag direction showing greater sensitivity than the armchair. As strain progresses, initial mono-vacancies evolve into more complex defects, hindering predictions of the mechanical response in certain cases. Lastly, strain rate sensitivity is evaluated, yielding values of 0.0485 and 0.0365 for the zigzag and armchair directions, respectively.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"134-139"},"PeriodicalIF":2.1,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic Analysis of the Effect of the Device-to-Device Variability of Real-World Memristors on the Implementation of Uncoupled Memristive Cellular Nonlinear Networks 真实忆阻器器件间变异性对非耦合忆阻细胞非线性网络实现影响的动态分析

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2025-02-24 DOI: 10.1109/TNANO.2025.3545251

Yongmin Wang;Kristoffer Schnieders;Vasileios Ntinas;Alon Ascoli;Felix Cüppers;Susanne Hoffmann-Eifert;Stefan Wiefels;Ronald Tetzlaff;Vikas Rana;Stephan Menzel

{"title":"Dynamic Analysis of the Effect of the Device-to-Device Variability of Real-World Memristors on the Implementation of Uncoupled Memristive Cellular Nonlinear Networks","authors":"Yongmin Wang;Kristoffer Schnieders;Vasileios Ntinas;Alon Ascoli;Felix Cüppers;Susanne Hoffmann-Eifert;Stefan Wiefels;Ronald Tetzlaff;Vikas Rana;Stephan Menzel","doi":"10.1109/TNANO.2025.3545251","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3545251","url":null,"abstract":"Cellular Nonlinear Networks (CNNs) are a well established computing approach in the domain of analog computing, known for massive parallelism and data processing locality that enable efficient hardware implementations. Combining CNN with non-volatile memristive devices holds the promise to overcome technological hurdles, like scalability issues, and high energy consumption, while also introducing richer dynamics into the field of CNN. Memristive devices based on the valence change mechanism (VCM) show great properties, like bipolar switching, tuneable resistance and non-volatility that are essential for the design of memristive CNN (M-CNN). In this study we design and investigate an uncoupled M-CNN cell implementing the EDGE detection task. This is the first paper investigating the resilience of M-CNN against device-to-device variability. To this end the first experimentally acquired Dynamic Route Map (DRM) of the M-CNN cell is employed. The comparison with simulations results allows for investigating the effect of mechanisms in the VCM device on the performance of the cell. The result of the computation is stored in the VCM device despite the unavoidable variability in the electrical behaviors of different device samples. Furthermore, the theoretically predicted richer dynamics of M-CNNs over traditional CNNs is demonstrated. This work provides crucial insights into design considerations of M-CNNs, especially as here first steps towards the comprehensive analysis on the effect of imperfections and variability of the memristor on M-CNN cell are taken.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"121-128"},"PeriodicalIF":2.1,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0