Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang
{"title":"Research on Photovoltaic Measurement and Electrochemical Impedance Spectroscopy Analysis of Dye-Sensitized Solar Cells With Modification of Photoanodes by TiO2 Nanofibers Composited With Zn2SnO4-SnO2 Under Various Illuminances","authors":"Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang","doi":"10.1109/TNANO.2024.3460869","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3460869","url":null,"abstract":"This study involves the utilization of electrostatic access techniques and the development of ZTO-SnO\u0000<sub>2</sub>\u0000/TiO\u0000<sub>2</sub>\u0000 nanofibers (NFs) in different ratios of 1%, 3%, and 5%. The dye-sensitized solar cells (DSSCs) efficiency was enhanced through the utilization of ZTO-SnO\u0000<sub>2</sub>\u0000 nanofiber composites in photoanodes. According to this study, the 3% ZTO-SnO\u0000<sub>2</sub>\u0000/TiO\u0000<sub>2</sub>\u0000 nanofiber-modified DSSCs conversion efficiency was better than that of other DSSCs at different light intensities. When the light intensity is 100 mW/cm\u0000<sup>2</sup>\u0000, there is a rise in efficiency by 30.91% compared with pure TiO\u0000<sub>2</sub>\u0000. The EIS (Electrochemical Impedance Spectroscopy) usage demonstrated that adding ZTO-SnO\u0000<sub>2</sub>\u0000 efficiently lowered the photoanode's electron transfer impedance. The higher scattering potential and powerful electron transfer capability have been demonstrated to have a positive effect on increasing the JSC of DSSCs using quantum efficiency studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"684-691"},"PeriodicalIF":2.1,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact and Efficient Transverse Spliced Waveguide Grating Antenna for Integrated Optical Phased Array","authors":"Diksha Maurya;Devendra Chack;G. Vickey","doi":"10.1109/TNANO.2024.3459472","DOIUrl":"10.1109/TNANO.2024.3459472","url":null,"abstract":"Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"665-672"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduced Graphene Oxide-Polydimethylsiloxane Based Flexible Dry Electrodes for Electrophysiological Signal Monitoring","authors":"Suraj Baloda;Sashank Krishna Sriram;Sumitra Singh;Navneet Gupta","doi":"10.1109/TNANO.2024.3459931","DOIUrl":"10.1109/TNANO.2024.3459931","url":null,"abstract":"Graphene-based dry electrodes have shown considerable promise in electrophysiological signal monitoring applications by providing a comfortable, irritant-free alternative to traditional wet electrodes. The proposed electrode was fabricated using a spray-coating technique by depositing reduced graphene oxide (rGO) on a polydimethylsiloxane (PDMS) substrate. The rGO/PDMS dry electrodes exhibit the capability to capture and transmit weak bio-electrical signals such as Electrocardiogram (ECGs) and Electromyogram (EMGs) without significant attenuation or distortion. Experimental results show that when compared to conventional wet Ag/AgCl electrodes, the fabricated rGO/PDMS electrodes measure higher-quality ECG signals with improved SNRs while offering similar contact quality and electrode-skin impedance despite being a dry electrode. The fabricated rGO/PDMS electrodes demonstrated excellent performance and applicability making them suitable for use in wearable long-term health monitoring devices.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"644-651"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10679620","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury
{"title":"MXene- and Graphene-Assisted THz Metamaterial for Cancer Cells Detection Based on Refractive Index Sensing","authors":"Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury","doi":"10.1109/TNANO.2024.3458427","DOIUrl":"10.1109/TNANO.2024.3458427","url":null,"abstract":"An ultrathin metasurface-based polarization-insensitive single-band terahertz (THz) sensor comprising graphene concentric rings and a thin layer of MXene was investigated for the human body cancer cells detection. The overall metamaterial configuration exhibits single narrow-band nearly-perfect absorption with a high value of quality factor due to a full-width-half-maximum of 0.033 THz at the resonance frequency of 3.793 THz. The results show a high sensitivity of the metamaterial configuration along with a stable operation under different incidence polarizations. The results reveal the designed structure is of potential in biomedical applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"652-657"},"PeriodicalIF":2.1,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han
{"title":"A Review of Ising Machines Implemented in Conventional and Emerging Technologies","authors":"Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han","doi":"10.1109/TNANO.2024.3457533","DOIUrl":"10.1109/TNANO.2024.3457533","url":null,"abstract":"Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"704-717"},"PeriodicalIF":2.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori
{"title":"Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TNANO.2024.3445455","DOIUrl":"10.1109/TNANO.2024.3445455","url":null,"abstract":"Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of \u0000<inline-formula><tex-math>$9times$</tex-math></inline-formula>\u0000 and energy consumption by a factor of \u0000<inline-formula><tex-math>$300times$</tex-math></inline-formula>\u0000, while still achieving comparable predictive performance and uncertainty estimates compared to related works.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"636-643"},"PeriodicalIF":2.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design","authors":"Jungyoun Kwak;Gihun Choe;Shimeng Yu","doi":"10.1109/TNANO.2024.3447020","DOIUrl":"10.1109/TNANO.2024.3447020","url":null,"abstract":"A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V\u0000<sub>GS</sub>\u0000 = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"622-628"},"PeriodicalIF":2.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stochastic-Binary Hybrid Spatial Coding Multiplier for Convolutional Neural Network Accelerator","authors":"Yakun Zhou;Jiajun Yan;Yizhuo Zhou;Ziyang Shao;Jienan Chen","doi":"10.1109/TNANO.2024.3444278","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3444278","url":null,"abstract":"Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"600-605"},"PeriodicalIF":2.1,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Machine Learning-Based Compact Modeling of Silicon Cold Source Field-Effect Transistors","authors":"Haoqing Xu;Weizhuo Gan;Shujin Guo;Shengli Zhang;Zhenhua Wu","doi":"10.1109/TNANO.2024.3442476","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3442476","url":null,"abstract":"The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"615-621"},"PeriodicalIF":2.1,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz
{"title":"Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing","authors":"Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz","doi":"10.1109/TNANO.2024.3438542","DOIUrl":"10.1109/TNANO.2024.3438542","url":null,"abstract":"Energy-efficient sense amplifier (SA) circuits are essential for reliable detection of stored memory states in emerging memory systems. In this work, we introduce three novel sense amplifier topologies based on phase transition materials (PTM) in addition to the previously proposed one, collectively analyzing all four designs tailored for non-volatile memory applications. We utilize the abrupt switching and volatile hysteretic characteristics of PTMs which enables efficient and fast sensing operation in our proposed SA topologies. We provide comprehensive details of their functionality and assess how process variations impact their performance metrics. Our proposed sense amplifier topologies manifest notable performance enhancement. We achieve a ∼67% reduction in sensing delay and a ∼80% decrease in sensing power for current sensing. For voltage sensing, we achieve a ∼75% reduction in sensing delay and a ∼33% decrease in sensing power. Moreover, the proposed SA topologies exhibit improved variation robustness compared to conventional SAs. We also scrutinize the dependence of transistor mirroring window and PTM transition voltages on several device parameters to determine the optimum operating conditions and stance of tunability for each of the proposed SA topologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"606-614"},"PeriodicalIF":2.1,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141945961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}