Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays

Abstract

Artificial Intelligence (AI) has advanced to the stage where modern problems can be transformed into AI problems with computational costs. Increased complexity has exponentially raised computation and inference demands, primarily due to Von Neumann architecture limitations. In-memory computing (IMC) revolutionizes this paradigm by eliminating memory read-write overheads. Notably, the utilization of Resistive Random Access Memory (RRAM) in vector-matrix multiplication (VMM) configurations within IMC architectures has demonstrated substantial performance enhancements. In the proposed work, utilizing Digital-to-Time Converters (DTCs) and Time-to-Digital Converters (TDCs) optimizes hardware resources substantially within in-memory computing (IMC) architectures. Our proposed DTC and TDC blocks exhibit power consumptions of $41\ \mu \text{W}$ and $38\ \mu \text{W}$ and delays of $896\ \text{ps}$ and $530\ \text{ps}$. Additionally, we introduce a $4T-1R$ structure with Reset Stop Block (RSB) that facilitates 2-bit RRAM reprogramming and entails a latency of $1.07\ \mu \text{s}$ and energy/cell of $0.11\ \text{pJ}$. The overall energy efficiency of Time-Domain VMM (TDVMM) architecture is $866.6\ \text{Tops/W}$, which is $1.61 \times$ more efficient than contemporary TDVMMs. Furthermore, our design consistently performs with a cycle-to-cycle variability of 23%, showcasing its tolerance to variations.