IEEE Transactions on Nanotechnology最新文献_第5页

Modeling and Simulation of Correlated Cycle-to- Cycle Variability in the Current-Voltage Hysteresis Loops of RRAM Devices RRAM 器件电流-电压滞后环中相关周期变化的建模与仿真

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-10-23 DOI: 10.1109/TNANO.2024.3485213

E. Salvador;M.B. Gonzalez;F. Campabadal;R. Rodriguez;E. Miranda

{"title":"Modeling and Simulation of Correlated Cycle-to- Cycle Variability in the Current-Voltage Hysteresis Loops of RRAM Devices","authors":"E. Salvador;M.B. Gonzalez;F. Campabadal;R. Rodriguez;E. Miranda","doi":"10.1109/TNANO.2024.3485213","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3485213","url":null,"abstract":"Resistive RAMs or memristors are nowadays considered serious candidates for the implementation of energy efficient and scalable neuromorphic computing systems. However, a major drawback of this technology is the instability of the device current-voltage (I-V) characteristic as is clearly revealed by the so-called cycle-to-cycle (C2C) variability. This lack of complete reproducibility is a consequence of the spontaneous or induced morphological changes of the filamentary conducting structure occurring at atomic level. Variability is an essential issue any compact model for the conduction characteristics of RRAM devices should be able to cope with to be considered realistic. In this work, a thorough investigation of the C2C variability in the I-V loops of HfO\u00002\u0000-based memristive structures was carried out with the aim of incorporating this information into the equations of the Dynamic Memdiode Model. From the compact modeling viewpoint, C2C correlation effects are achieved using model parameters expressed as mean-reverting stochastic processes driven by Wiener noise (Ornstein-Uhlenbeck process). The direct and indirect links between the random behavior of the model parameters and the observable magnitudes (high and low resistance states, set and reset voltages, etc.) are discussed. The agreement between simulation and experimental results is statistically assessed using the Wasserstein's distance metric.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"758-764"},"PeriodicalIF":2.1,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10730782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low Temperature One-Pot Synthesis of rGO Nanorod-PVDF Composite and Fabrication of a Thin Film Solid-State Fractional Order Device rGO 纳米棒-PVDF 复合材料的低温一锅合成及薄膜固态分数阶器件的制作

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-27 DOI: 10.1109/TNANO.2024.3469973

Manas R. Samantaray;Agniv Tapadar;Santanu Das;Nikhil Chander;Avishek Adhikary

{"title":"Low Temperature One-Pot Synthesis of rGO Nanorod-PVDF Composite and Fabrication of a Thin Film Solid-State Fractional Order Device","authors":"Manas R. Samantaray;Agniv Tapadar;Santanu Das;Nikhil Chander;Avishek Adhikary","doi":"10.1109/TNANO.2024.3469973","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3469973","url":null,"abstract":"This work proposes a novel, cost-effective, and simplified method to fabricate(reduced graphene oxide (rGO) nanorods. It is demonstrated that when a composite film made of polyvinylidene fluoride (PVDF) and the fabricated rGO is formed on a silver substrate, a unique structural morphology appears. This structure is unlike the general morphological structures of PVDF and rGO. The fabricated rGO has a nanorod-shapes of 0.54 nm to 1.15 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m length and diameter in the 51\u0000<inline-formula><tex-math>$-$</tex-math></inline-formula>\u0000 64 nm range. The presence of \u0000<inline-formula><tex-math>$alpha$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$beta$</tex-math></inline-formula>\u0000 phase PVDF and rGO in the composite has been confirmed using both X-ray diffractometer and Raman spectroscopy. Impedance characterization of the fabricated device shows constant phase characteristics in the frequency range of 126 kHz to 2 MHz with a constant phase angle at \u0000<inline-formula><tex-math>$-63^{circ }$</tex-math></inline-formula>\u0000 to \u0000<inline-formula><tex-math>$-78^{circ }$</tex-math></inline-formula>\u0000. This indicates that the proposed rGO Nanorod-PVDF composite is suitable for the fabrication of a thin film fractor (fractional order device) with fractional order \u0000<inline-formula><tex-math>$eta$</tex-math></inline-formula>\u0000 = 0.70 to 0.88 and fractance value 0.08 to 3.08 nF\u0000<inline-formula><tex-math>$s^{eta }$</tex-math></inline-formula>\u0000.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"692-695"},"PeriodicalIF":2.1,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

First Realization of Batch Normalization in Flash-Based Binary Neural Networks Using a Single Voltage Shifter 使用单电压变换器首次实现基于闪存的二进制神经网络批量归一化

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-23 DOI: 10.1109/TNANO.2024.3466128

Sungmin Hwang;Wangjoo Lee;Jeong Woo Park;Dongwoo Suh

{"title":"First Realization of Batch Normalization in Flash-Based Binary Neural Networks Using a Single Voltage Shifter","authors":"Sungmin Hwang;Wangjoo Lee;Jeong Woo Park;Dongwoo Suh","doi":"10.1109/TNANO.2024.3466128","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3466128","url":null,"abstract":"Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO\u00002\u0000/Si\u00003\u0000N\u00004\u0000/SiO\u00002\u0000. The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary \u0000<italic>LeNet-5\u0000 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"677-683"},"PeriodicalIF":2.1,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pioneering Multi-Functionality through VO2-Infused Polarization Insensitive Conformal Meta-Structures in Terahertz Regime 通过注入 VO2 的极化不敏感共形元结构，率先实现太赫兹波段的多功能性

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-17 DOI: 10.1109/TNANO.2024.3462802

Aks Raj;Ravi Kumar Gangwar;Raghvendra Kumar Chaudhary

引用次数: 0

Research on Photovoltaic Measurement and Electrochemical Impedance Spectroscopy Analysis of Dye-Sensitized Solar Cells With Modification of Photoanodes by TiO2 Nanofibers Composited With Zn2SnO4-SnO2 Under Various Illuminances 用 Zn2SnO4-SnO2 复合 TiO2 纳米纤维修饰光阳极的染料敏化太阳能电池在各种光照条件下的光伏测量和电化学阻抗谱分析研究

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-16 DOI: 10.1109/TNANO.2024.3460869

Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang

{"title":"Research on Photovoltaic Measurement and Electrochemical Impedance Spectroscopy Analysis of Dye-Sensitized Solar Cells With Modification of Photoanodes by TiO2 Nanofibers Composited With Zn2SnO4-SnO2 Under Various Illuminances","authors":"Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang","doi":"10.1109/TNANO.2024.3460869","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3460869","url":null,"abstract":"This study involves the utilization of electrostatic access techniques and the development of ZTO-SnO\u00002\u0000/TiO\u00002\u0000 nanofibers (NFs) in different ratios of 1%, 3%, and 5%. The dye-sensitized solar cells (DSSCs) efficiency was enhanced through the utilization of ZTO-SnO\u00002\u0000 nanofiber composites in photoanodes. According to this study, the 3% ZTO-SnO\u00002\u0000/TiO\u00002\u0000 nanofiber-modified DSSCs conversion efficiency was better than that of other DSSCs at different light intensities. When the light intensity is 100 mW/cm\u00002\u0000, there is a rise in efficiency by 30.91% compared with pure TiO\u00002\u0000. The EIS (Electrochemical Impedance Spectroscopy) usage demonstrated that adding ZTO-SnO\u00002\u0000 efficiently lowered the photoanode's electron transfer impedance. The higher scattering potential and powerful electron transfer capability have been demonstrated to have a positive effect on increasing the JSC of DSSCs using quantum efficiency studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"684-691"},"PeriodicalIF":2.1,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact and Efficient Transverse Spliced Waveguide Grating Antenna for Integrated Optical Phased Array 用于集成光学相控阵的紧凑高效横向拼接波导光栅天线

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-12 DOI: 10.1109/TNANO.2024.3459472

Diksha Maurya;Devendra Chack;G. Vickey

{"title":"Compact and Efficient Transverse Spliced Waveguide Grating Antenna for Integrated Optical Phased Array","authors":"Diksha Maurya;Devendra Chack;G. Vickey","doi":"10.1109/TNANO.2024.3459472","DOIUrl":"10.1109/TNANO.2024.3459472","url":null,"abstract":"Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"665-672"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MXene- and Graphene-Assisted THz Metamaterial for Cancer Cells Detection Based on Refractive Index Sensing 基于折射率传感的 MXene 和石墨烯辅助太赫兹超材料用于检测癌细胞

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-11 DOI: 10.1109/TNANO.2024.3458427

Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury

引用次数: 0

A Review of Ising Machines Implemented in Conventional and Emerging Technologies 传统和新兴技术中的伊辛机综述

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-10 DOI: 10.1109/TNANO.2024.3457533

Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han

{"title":"A Review of Ising Machines Implemented in Conventional and Emerging Technologies","authors":"Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han","doi":"10.1109/TNANO.2024.3457533","DOIUrl":"10.1109/TNANO.2024.3457533","url":null,"abstract":"Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"704-717"},"PeriodicalIF":2.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation Spatial-SpinDrop: 利用自旋电子学实现基于空间剔除的二元贝叶斯神经网络

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-09-06 DOI: 10.1109/TNANO.2024.3445455

Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori

{"title":"Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TNANO.2024.3445455","DOIUrl":"10.1109/TNANO.2024.3445455","url":null,"abstract":"Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of \u0000<inline-formula><tex-math>$9times$</tex-math></inline-formula>\u0000 and energy consumption by a factor of \u0000<inline-formula><tex-math>$300times$</tex-math></inline-formula>\u0000, while still achieving comparable predictive performance and uncertainty estimates compared to related works.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"636-643"},"PeriodicalIF":2.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design 在单片式三维集成电路设计中实现堆叠纳米氧化物通道晶体管的设计-技术协同优化

IF 2.1 4区工程技术

IEEE Transactions on Nanotechnology Pub Date : 2024-08-21 DOI: 10.1109/TNANO.2024.3447020

Jungyoun Kwak;Gihun Choe;Shimeng Yu

引用次数: 0