Simulation Study on the Impact of Miniaturization in 3 nm Node 3D Junctionless Transistors

Abstract

Junctionless Nanosheet gate-all-around Field Effect Transistor (JL-NSGAAFET) is a promising technology characterized by the absence of any junctions between source-channel-drain. This absence allows to further scale down transistors while limiting short-channel effects. In this article, JL-NSGAAFET is explored as a potential candidate for the next 3 nm technology node through 3D TCAD simulations. First, we propose and simulate, through fabrication process simulations, a fabrication strategy for the JL-NSGAAFET compatible with the current manufacturing technology and based on the inversion mode NSGAAFET fabrication process. The high-k gate dielectric (HfO₂) and metal-gate technology (TiN) are also adopted in the fabrication process to enhance the electrostatic gate control over the channel for the n-type and p-type transistors. Then, we perform electrical simulations of the device by also including drift-diffusion model and quantum density gradient correction. We characterize the device in terms of electrical performance and compare with the conventional NSGAAFET. Furthermore, to investigate the impact of the device scaling on the unwanted short channel effects, we simulate and analyze the devices while varying the gate length (L_G) from 20 nm to 12 nm. Our reported simulation results prove that JL-NSGAAFET exhibits near-ideal subthreshold slope, low drain-induced barrier lowering (DIBL) and high on-to-off current ratio (I_ON/I_OFF) with superior advantages of greater drive currents and a simpler fabrication process because of the absence of junctions.