Polynomial Formal Verification of a RISC-V Processor

IF 2.1 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Nanotechnology Pub Date : 2025-03-05 DOI:10.1109/TNANO.2025.3548265

Lennart Weingarten;Kamalika Datta;Rolf Drechsler

引用次数: 0

Abstract

Verification plays a major role in ensuring the functional correctness of any design. In recent years with growing complexity of processor designs, verification has assumed utmost importance. Simulation-based techniques cannot ensure completeness in verification, and in this regard formal methods prove crucial. Although formal methods guarantee completeness it is hard to quantify the exact time and space complexities. Recently some works have demonstrated that it is possible to achieve polynomial space and time complexities for various arithmetic circuits as well as for processors. In this paper we propose a Binary Decision Diagram (BDD) based Polynomial Formal Verification (PFV) approach for verifying processors. As a case study, we discuss the PFV for a multi-cycle processor (viz., MicroRV32) with support for combinational and sequential sub-systems. New data structures and code base are utilized to verify all the functional components. Experimental results reveal that the verification can indeed be performed in polynomial time.

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验证在确保任何设计的功能正确性方面都发挥着重要作用。近年来，随着处理器设计的复杂性不断增加，验证变得极为重要。基于仿真的技术无法确保验证的完整性，在这方面，形式化方法被证明是至关重要的。虽然形式化方法能保证完整性，但很难量化确切的时间和空间复杂性。最近的一些研究表明，各种算术电路和处理器都有可能实现多项式空间和时间复杂性。在本文中，我们提出了一种基于二进制判定图（BDD）的多项式形式化验证（PFV）方法，用于验证处理器。作为案例研究，我们讨论了支持组合和顺序子系统的多周期处理器（即 MicroRV32）的 PFV。新的数据结构和代码库用于验证所有功能组件。实验结果表明，验证确实可以在多项式时间内完成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Nanotechnology 工程技术-材料科学：综合

CiteScore

4.80

自引率

8.30%

发文量

审稿时长

8.3 months

期刊介绍： The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.