Development of SRAM in 3-Dimensional Stacked FET With Direct Backside Contact Beyond 1Nm Node

Abstract

Among the various Backside Interconnections (BSI) methods, Direct Backside Contact (DBC) is essential in minimizing the area of logic standard cells and SRAM bitcells with 3-dimensional Stacked FETs (3DSFET) beyond the 1 nm node. Additionally, from an SRAM design perspective, the DBC structure offers the advantage of allowing the use of NMOS for the Pass-Gate (PG) transistor, as was done previously. In this study, we demonstrated SRAM transistors operation by adopting the highly promising 3DSFET with DBC structure. And we validated the SRAM bitcell operation through TCAD simulation by applying hardware verification of the SRAM transistor. As a result, we can propose an innovative structure that is compatible with both logic transistor performance and SRAM bitcell configuration beyond 1 nm node.