{"title":"Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias","authors":"Y. Luo, J. Orona, D. Nayak, D. Gitlin","doi":"10.1109/RELPHY.2007.369903","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369903","url":null,"abstract":"A new mechanism for PMOS NBTI (negative biased temperature instability) with drain bias is presented. The turnaround behavior of device degradation is explained. While drain bias reduces gate oxide voltage and causes less NBTI, the channel-hot-hole enhances the NBTI degradation. For the first time, a semi-empirical model is proposed that fits well with the experimental data, including various parameters, such as temperature, voltage, channel length, and drive current.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Ju, S.C. Song, T. Lee, B. Sassman, C. Kang, B. Lee, R. Jammy
{"title":"Effect of in situ plasma treatment on high-k films after high-k removal with plasma etching from the S/D region","authors":"B. Ju, S.C. Song, T. Lee, B. Sassman, C. Kang, B. Lee, R. Jammy","doi":"10.1109/RELPHY.2007.369563","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369563","url":null,"abstract":"In this work, a plasma etch technique for removing high-k dielectric from the source and drain (S/D) areas after metal/high-k gate stack patterning has been developed. To cure the plasma damage induced during the plasma etch of high-k films, an in situ plasma treatment with O2 or N2 was applied to several high-k compositions. This plasma process induces no structural weaknesses and exhibits excellent electrical performance (gate leakage current, Ion/Ioff ratio, gate-induced drain leakage, and threshold voltage distribution) after an in situ plasma (O2) treatment. Therefore, the results indicate that this plasma etch process is suitable for low power and high performance CMOS applications, particularly in short channel devices.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Mitrofanov, T. Siegrist, D. Lang, C. Kloc, W. So, M. Sergent, A. P. Ramirez
{"title":"Defects in Organic Molecular Crystals: Spectroscopy and Effects on Electronic and Optical Properties","authors":"O. Mitrofanov, T. Siegrist, D. Lang, C. Kloc, W. So, M. Sergent, A. P. Ramirez","doi":"10.1109/RELPHY.2007.369898","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369898","url":null,"abstract":"Transport and optical properties of organic molecular crystals depend on the presence and distribution of crystallographic defects. In this paper we overview the impact of defects on properties of single crystal rubrene, an organic material with the highest to date hole mobility. We show that the defects strongly affect the mobility and carrier concentration in rubrene.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131796098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of Surface Cleaning on Stressvoiding and Electromigration of Cu Damascene Interconnection","authors":"Jen-Pan Wang, Y. Su, J.F. Chen","doi":"10.1109/RELPHY.2007.369993","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369993","url":null,"abstract":"This paper is to study the influence of Cu surface clean process on stressvoiding and electromigration of Cu dual damascene metallization. A superior Cu pre-cleaning process condition is developed to improve Cu stress-induced voiding (SIV) and electromigration (EM). Higher pre-clean bias-power and shorter pre-clean time demonstrate remarkable low via resistance and excellent Cu reliability performance.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Critical Gate Voltage Triggering Irreversible Gate Dielectric Degradation","authors":"V. Lo, K. Pey, C. Tung, D. Ang","doi":"10.1109/RELPHY.2007.369958","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369958","url":null,"abstract":"Using a multiple-stage constant-voltage stress (M-CVS) methodology, a critical gate voltage (V<sub>crit</sub>) is found to demarcate the post-breakdown (BD) gate leakage current (I<sub>g</sub>) evolution. For a gate voltage (V<sub>g</sub>) < V<sub>crit</sub>, I<sub>g</sub> digitally fluctuates with no apparent net increase. For V<sub>g</sub> > V<sub>crit</sub>, I<sub>g</sub> rapidly evolves into a stable high leakage state. V<sub>crit</sub> is found to decrease with decreasing oxide thickness (T<sub>ox</sub>), implying that it has a significant impact on I<sub>g</sub> degradation rate (dl<sub>g</sub>/dt) (Lombardo, 2003) at nominal operating voltages.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ballistic phonon enhanced NBTI","authors":"Y. Wang, P. Cheung, A. Oates, P. Mason","doi":"10.1109/RELPHY.2007.369902","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369902","url":null,"abstract":"Advanced integrated circuit has thermal energy removal issue due to heat dissipated by current at the drain junction of MOSFET. This is a problem only when millions of transistors are generating the thermal energy. In sub-100nm CMOS technology where the transistor channel lengths are smaller than the phonon scattering mean-free-path, a new kind of drain junction heating problem arises due to ballistic phonon effect. This new heating problem exists even when there is only one transistor operating. The impact of this new heating phenomenon on long term reliability of transistor is examined for the first time here. We show that NBTI in pMOS is severely worsened.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jung-Geun Jee, W. Kwon, Woong Lee, Jung-Hyun Park, Hyeong-Ki Kim, Ho-Min Son, Wonjong Chang, Jae-Jong Han, Y. Hyung, Hyeon-deok Lee
{"title":"Development and Optimization of Re-Oxidized Tunnel Oxide with Nitrogen Incorporation for the Flash Memory Applications","authors":"Jung-Geun Jee, W. Kwon, Woong Lee, Jung-Hyun Park, Hyeong-Ki Kim, Ho-Min Son, Wonjong Chang, Jae-Jong Han, Y. Hyung, Hyeon-deok Lee","doi":"10.1109/RELPHY.2007.369890","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369890","url":null,"abstract":"The reliability properties of NOR flash memory with 65nm node being developed in Samsung electronics are greatly improved by using the newly proposed re-oxidized tunnel oxide. Especially, by optimizing the process variables such as the re-oxidation thickness/time, the partial pressure of NO during annealing, and the kinds of re-oxidizing materials, the Vth shifts post cycling and after post-cycling bake were decreased to the level of 28% and 42% of conventional NO annealed tunnel oxide, respectively.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116216246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization of Degradation of 65nm Node via Chains and Single Vias","authors":"X. Federspiel, S. Courtas, M. Grégoire","doi":"10.1109/RELPHY.2007.369990","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369990","url":null,"abstract":"We used the resistance increase of single via to determine the intrinsic degradation kinetics of via in the temperature range 175 to 325C. The evolution of resistance in time follows a parabolic regime up to 325C, with activation energy of 1.0eV. It is worth noting that the evolution of degradation kinetics with temperature follows a simple Arrhenius equation. Thus, there is no evidence for an effect of thermo elastic stress on the degradation kinetics. We showed that the degradation mechanism in chains and single vias is similar. It is also noticeable that we found a bimodal distribution of resistance increase that is not visible from measurement of via chains. Together with making FA easier, this demonstrates the benefit of using single via to characterize stress voiding.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122934976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reverse-Body Biasing for Radiation-Hard by Design Logic Gates","authors":"L. Clark, K.C. Mohr, K. Holbert","doi":"10.1109/RELPHY.2007.369961","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369961","url":null,"abstract":"Different radiation hardening by design techniques for mitigating total ionizing dose (TID) effects in NMOS transistors are presented. NMOS annular layout transistors are compared to two-edge and hardened by reverse-body bias (RBB) with respect to CMOS gate area, delay, active and leakage power, and TID hardness. Accelerated testing using Co-60 irradiation of test structures on a 130 nm bulk CMOS process shows that RBB provides smaller devices and allows less chip-level leakage at 1 Mrad(Si) than a design hardened using annular gates has pre-irradiation. Simulations of fanout-of-four (FO4) two-input NAND gates show that RBB provides an energy-delay product (EDP) comparable to conventional two-edge gates. Different annular topologies have EDP 35% to over 350% greater","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128276366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kontos, R. Gauthier, K. Chatty, K. Domanskr, M. Muhammad, C. Seguin, R. Halbach
{"title":"External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies","authors":"D. Kontos, R. Gauthier, K. Chatty, K. Domanskr, M. Muhammad, C. Seguin, R. Halbach","doi":"10.1109/RELPHY.2007.369915","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369915","url":null,"abstract":"External latchup phenomena in 65nm CMOS technology under transient events are studied. The effect of different design schemes such as injector to detector spacing, detector orientation, guardring protection strategy and also process factors such as wafer resistivity are investigated. The distance of latchup structures from injector devices inside I/O cells is found to be crucial for the latchup robustness of hardware. Guardring protection strategies with second guardring surrounding the latchup structure are proven to be more robust than that of a single guardring. The substrate resistivity can have a very strong impact to the latchup characteristics of hardware. For distances beyond 5mum between latchup structure and injection device is one of the key factors determining the latchup triggering current levels.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126210936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}