External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

Abstract

External latchup phenomena in 65nm CMOS technology under transient events are studied. The effect of different design schemes such as injector to detector spacing, detector orientation, guardring protection strategy and also process factors such as wafer resistivity are investigated. The distance of latchup structures from injector devices inside I/O cells is found to be crucial for the latchup robustness of hardware. Guardring protection strategies with second guardring surrounding the latchup structure are proven to be more robust than that of a single guardring. The substrate resistivity can have a very strong impact to the latchup characteristics of hardware. For distances beyond 5mum between latchup structure and injection device is one of the key factors determining the latchup triggering current levels.