Effect of in situ plasma treatment on high-k films after high-k removal with plasma etching from the S/D region

Abstract

In this work, a plasma etch technique for removing high-k dielectric from the source and drain (S/D) areas after metal/high-k gate stack patterning has been developed. To cure the plasma damage induced during the plasma etch of high-k films, an in situ plasma treatment with O2 or N2 was applied to several high-k compositions. This plasma process induces no structural weaknesses and exhibits excellent electrical performance (gate leakage current, Ion/Ioff ratio, gate-induced drain leakage, and threshold voltage distribution) after an in situ plasma (O2) treatment. Therefore, the results indicate that this plasma etch process is suitable for low power and high performance CMOS applications, particularly in short channel devices.