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Proceedings International Conference on Microelectronic Test Structures最新文献

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Three-port RF characterization of foundry dual-gate FETs using two-port test structures with on-chip loading resistors 采用片上负载电阻的双端口测试结构对铸造双栅场效应管的三端口射频特性进行研究
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513966
U. Lott, W. Baumberger, Urs Gisiger
{"title":"Three-port RF characterization of foundry dual-gate FETs using two-port test structures with on-chip loading resistors","authors":"U. Lott, W. Baumberger, Urs Gisiger","doi":"10.1109/ICMTS.1995.513966","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513966","url":null,"abstract":"Special test structures for the three-port linear RF characterization of dual-gate FETs using on-chip integrated 50 ohm load resistors for the third port are described. These test structures allow us to characterize dual-gate FETs with a standard two-port network analyzer and only two wafer probes. Measurement results of test FETs realized on a commercial GaAs foundry MESFET process show that good accuracy of the three-port S-parameters is achieved.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128797949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A test chip for MOS transistor capacitance characterization 一种MOS晶体管电容特性测试芯片
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513961
R. Lorival, P. Nouet
{"title":"A test chip for MOS transistor capacitance characterization","authors":"R. Lorival, P. Nouet","doi":"10.1109/ICMTS.1995.513961","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513961","url":null,"abstract":"We present test chip for the capacitive characterization of MOS transistors. It allows one to measure accurately capacitances of the transistor and to identify the various components (i.e. gate-source, gate-bulk and gate-drain). From capacitance measurements, it is then possible to determine effective dimensions of the transistor (length and width) as well as gate oxide thickness. As Test Structures enable the measurement of very small capacitances, minimum dimension transistors are studied.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new technique for measuring threshold voltage distribution in flash EEPROM devices 一种测量闪存EEPROM器件阈值电压分布的新技术
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513988
T. Himeno, N. Matsukawa, H. Hazama, K. Sakui, M. Oshikiri, K. Masuda, K. Kanda, Y. Itoh, J. Miyamoto
{"title":"A new technique for measuring threshold voltage distribution in flash EEPROM devices","authors":"T. Himeno, N. Matsukawa, H. Hazama, K. Sakui, M. Oshikiri, K. Masuda, K. Kanda, Y. Itoh, J. Miyamoto","doi":"10.1109/ICMTS.1995.513988","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513988","url":null,"abstract":"A new, simple test circuit for evaluating the reliability of flash EEPROM devices is described. It measures threshold voltage (V/sub th/) distributions of a large number of cell transistors with easy static operation similar to I-V curve measurement. Moreover, each cell transistor in a large array is selectable to measure static characteristics. This circuit makes it possible to measure the V/sub th/ distribution even in the negative region after erase operation for a NAND-type EEPROM.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Modified transmission line pulse system and transistor test structures for the study of ESD 改进的传输线脉冲系统和用于ESD研究的晶体管测试结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513959
R. Ashton
{"title":"Modified transmission line pulse system and transistor test structures for the study of ESD","authors":"R. Ashton","doi":"10.1109/ICMTS.1995.513959","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513959","url":null,"abstract":"A modified Transmission Line Pulsing System for characterizing transistors under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure damage. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114897882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Precise measurement of P-N junction leakage current generated in Si subsurface 硅地下P-N结漏电流的精确测量
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513956
M. Horikawa, T. Mizutani, K. Noda, T. Kitano
{"title":"Precise measurement of P-N junction leakage current generated in Si subsurface","authors":"M. Horikawa, T. Mizutani, K. Noda, T. Kitano","doi":"10.1109/ICMTS.1995.513956","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513956","url":null,"abstract":"We present a new method of measuring junction leakage current generated only in the subsurface of the silicon substrate. In this method, diffusion current from deep in the bulk silicon is blocked, so the peripheral component of the junction leakage current was measured accurately, even at elevated temperatures. Using this new test device, we concluded that the leakage current generated in a denuded zone of Czochralski-grown Si is as small as that for an epitaxial layer.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes 利用带电荷收集电极的MOS电容器评价晶圆加工过程中的电荷积累
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513936
H. Kubo, T. Namura, K. Yoneda, H. Ohishi, Y. Todokoro
{"title":"Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes","authors":"H. Kubo, T. Namura, K. Yoneda, H. Ohishi, Y. Todokoro","doi":"10.1109/ICMTS.1995.513936","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513936","url":null,"abstract":"The charge build-up evaluation technique in semiconductor wafer processing such as ion implantation and plasma processing by using the MOS capacitor with charge collecting electrode (antenna) has been proposed. The estimation of charge build-up during ion implantation has been successfully demonstrated by using this technique. The charge detection sensitivity of a small area MOS capacitor can be improved by using the antenna structure. To estimate charge build-up quantitatively, gate oxide thickness, substrate type, capacitor area and antenna ratio should be carefully chosen. This technique is very useful to estimate charge build-up in conjunction with other charge build-up detection techniques such as EEPROM.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"280 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wafer-level electromigration tests on NIST and SWEAT structures NIST和SWEAT结构的晶圆级电迁移测试
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513978
F. Giroux, C. Gounelle, P. Mortini, G. Ghibaudo
{"title":"Wafer-level electromigration tests on NIST and SWEAT structures","authors":"F. Giroux, C. Gounelle, P. Mortini, G. Ghibaudo","doi":"10.1109/ICMTS.1995.513978","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513978","url":null,"abstract":"Wafer-level electromigration tests are carried out on NIST and SWEAT structures. Four different process splits are tested. For 300/spl deg/C maximum line temperature both structures allow detection of the differences in the process. On the other hand, for high maximum temperature no difference in process is observed by the electromigration tests. On the basis of these results, advantages and drawbacks of SWEAT and NIST structures are discussed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129085826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Source/drain junction leakage current of LDD NMOSFET with various spacer materials 不同间隔材料的LDD NMOSFET源极漏极漏电流
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513968
J. Om, M. Jo, Hyo-Sik Park, In-Sool Chung, W. Min
{"title":"Source/drain junction leakage current of LDD NMOSFET with various spacer materials","authors":"J. Om, M. Jo, Hyo-Sik Park, In-Sool Chung, W. Min","doi":"10.1109/ICMTS.1995.513968","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513968","url":null,"abstract":"The source/drain junction leakage currents of lightly doped drain (LDD) MOSFET for various gate sidewall spacer materials have been measured and analyzed. Since the step coverages of spacer materials and the etch rates of field oxide during the gate sidewall spacer etch process are different, the junction currents are found to be different for three spacer materials. Therefore, the corner defects formed at the boundaries between the source/drain substrate and the field oxide have different depth. The deeper the corner defects form, the more the junction leakage currents flow. The defects are generated by the damage from n/sup +/ source/drain As/sup 75/ implant process following the gate sidewall spacer etch.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129885332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct determination of base transit time for heterojunction bipolar transistors without cutoff frequency measurement 不测量截止频率的异质结双极晶体管基极传输时间的直接测定
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513957
Seonghearn Lee
{"title":"Direct determination of base transit time for heterojunction bipolar transistors without cutoff frequency measurement","authors":"Seonghearn Lee","doi":"10.1109/ICMTS.1995.513957","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513957","url":null,"abstract":"An accurate extraction method, based on a simple Z parameter equation at low frequencies, is developed to determine the base transit time of heterojunction bipolar transistors without cutoff frequency measurement that may suffer an inaccuracy. This new technique has much smaller uncertainty than the previous cutoff frequency method, because the determination of collector charging time is not needed to extract the base transit time using this method.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129031734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement of contact resistance distribution using a 4k contacts array 使用4k触点阵列测量触点电阻分布
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513945
T. Hamamoto, T. Ozaki, M. Aoki, Y. Ishibashi
{"title":"Measurement of contact resistance distribution using a 4k contacts array","authors":"T. Hamamoto, T. Ozaki, M. Aoki, Y. Ishibashi","doi":"10.1109/ICMTS.1995.513945","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513945","url":null,"abstract":"A new test structure suitable for measuring a contact resistance distribution has been developed. It includes the following two components: (1) a 256 row, 16 column (=4096) four-terminal cross-contact array; and (2) peripheral circuits, which consist of an eight-stage CMOS binary counter and 256 bit CMOS decoders. It was found that contact resistance can be fitted by a Gaussian distribution more than three standard deviations of the mean value. The relationships between the contact size and the standard deviation of the contact resistance has been discussed for two types of contacts: Al/TiN/TiSi/sub 2/-n+Si and WSi/sub 2//poly-n+Si. This test structure can simultaneously measure the series resistance of a two-terminal contact chain and the individual contact resistance. Comparing these results, it was found that the increase of the series resistance of the contact chain is due to the appearance of the contact that is outside of the Gaussian distribution.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127590337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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