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Proceedings International Conference on Microelectronic Test Structures最新文献

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An automated approach to wafer distribution analysis 晶圆分布分析的自动化方法
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513972
C. Perello, M. Lozano, J. Millan, E. Lora-Tamayo
{"title":"An automated approach to wafer distribution analysis","authors":"C. Perello, M. Lozano, J. Millan, E. Lora-Tamayo","doi":"10.1109/ICMTS.1995.513972","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513972","url":null,"abstract":"A set of statistical analysis techniques applied to parametric on-wafer testing are presented. The suitability of these techniques within an automated environment is emphasised, as an aid tool to control process stability and quality. The analysis includes a data filtering step where a central data distribution is assumed. The proposed filtering scheme tends to minimize the kurtosis and skewness of the parameter distribution. Proposed spatial analysis techniques applied to filtered data include data winsorizing, and first and second order momenta calculation. These statistics treat wafer non-homogeneities with a minimum amount of data as a counterpart to the classic 2D contour or 3D plot.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127994306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification 亚/spl μ m级并联多电平互连的新特性及其实验验证
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513946
K. Aoyama, K. Ise, H. Sato, K. Tsuneno, H. Masuda
{"title":"A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification","authors":"K. Aoyama, K. Ise, H. Sato, K. Tsuneno, H. Masuda","doi":"10.1109/ICMTS.1995.513946","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513946","url":null,"abstract":"This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121862246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A combined CBR-MOS gate structure for mobility and channel width extraction 结合CBR-MOS栅极结构的迁移率和通道宽度提取
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513987
J. Santander, M. Lozano, C. Cané, E. Lora-Tamayo
{"title":"A combined CBR-MOS gate structure for mobility and channel width extraction","authors":"J. Santander, M. Lozano, C. Cané, E. Lora-Tamayo","doi":"10.1109/ICMTS.1995.513987","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513987","url":null,"abstract":"A new test structure based on a Cross-Bridge-Resistor with the conducting layer made of the channel of a MOS transistor is presented. This structure has been fabricated in a CMOS technology, and the possibilities for extracting the carrier mobility and channel width without parasitic effects are analyzed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128849156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation 用于短沟道MOSFET特性评估的电栅长度测量测试结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513942
N. Kasai, I. Yamamoto, K. Koyama
{"title":"Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation","authors":"N. Kasai, I. Yamamoto, K. Koyama","doi":"10.1109/ICMTS.1995.513942","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513942","url":null,"abstract":"The electrical characteristics and gate lengths of individual MOSFETs are evaluated by a test structure with a Kelvin pattern as the gate electrode. The gate length measurement by SEM can be substituted by the electrical measurement using this test structure. Excellent correspondence is obtained between the threshold voltage lowering in the short channel region and the electrically measured gate length. Furthermore, the precision of drain-to-gate overlap length is improved by applying the effective channel length extraction method to the electrically measured gate length instead of the commonly used designed gate length.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An electrical test structure to evaluate linewidth variations due to proximity effects in optical lithography 一种用于评估光刻中由于接近效应而引起的线宽变化的电气测试结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513941
M. Fallon, J. Stevenson, A. Walton, A. Gundlach
{"title":"An electrical test structure to evaluate linewidth variations due to proximity effects in optical lithography","authors":"M. Fallon, J. Stevenson, A. Walton, A. Gundlach","doi":"10.1109/ICMTS.1995.513941","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513941","url":null,"abstract":"A simple test structure is used in the investigation of linewidth variation at topographical edges. Preliminary qualititative results for electrical linewidth variations are presented and correlated with SEM inspection. A linewidth reduction is observed as the two features on different layers draw closer together and it is demonstrated that this approach is sensitive enough to enable lithography engineers to optimise resist processing to minimise this effect.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133733385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Determination of solid solubility limit of In and Sb in Si using bonded silicon-on-insulator (SOI) substrate 用结合绝缘体上硅(SOI)衬底测定铟和锑在硅中的固溶极限
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513984
A. Sato, K. Suzuki, H. Horie, T. Sugii
{"title":"Determination of solid solubility limit of In and Sb in Si using bonded silicon-on-insulator (SOI) substrate","authors":"A. Sato, K. Suzuki, H. Horie, T. Sugii","doi":"10.1109/ICMTS.1995.513984","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513984","url":null,"abstract":"An SOI substrate enables us to obtain high, even distribution of impurity concentration in ion implantation with subsequent high-temperature annealing. We evaluated the solid solubility limit of In and Sb in Si by Hall measurement. We found that the solid solubility of In was constant at 1.5/spl times/10/sup 18/ cm/sup -3/ between 800/spl deg/C and 1100/spl deg/C, while that of Sb varied from 7/spl times/10/sup 19/ cm/sup -3/ at 800/spl deg/C to 1.2/spl times/10/sup 20/ cm/sup -3/ at 1100/spl deg/C, both of which were higher than previously reported values.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Statistical modeling tools, methods and applications for integrated circuit manufacturability 集成电路可制造性的统计建模工具、方法和应用
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513973
F. Iravani, M. Habu, E. Khalily
{"title":"Statistical modeling tools, methods and applications for integrated circuit manufacturability","authors":"F. Iravani, M. Habu, E. Khalily","doi":"10.1109/ICMTS.1995.513973","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513973","url":null,"abstract":"A description of various statistical modeling methods is provided. The analysis methods are discussed to remove the confusion in the existing literature. Statistical models are generated using factor analytic technique for SPICE level 3 on a 0.8 micron LDD CMOS. It is shown that our measurement based approach accurately predicts the device performance. We show that the existence of a \"physical MOS model\" is not a necessary pre-requisite to perform statistical modeling. Our approach provides models that are suitable for both analog and digital designs and promises to make statistical modeling feasible for general use.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Efficient extraction of metal parasitic capacitances 金属寄生电容的高效提取
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513964
G. J. Gaston, I.G. Daniels
{"title":"Efficient extraction of metal parasitic capacitances","authors":"G. J. Gaston, I.G. Daniels","doi":"10.1109/ICMTS.1995.513964","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513964","url":null,"abstract":"Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed. Recommendations are made for optimum test structure design and it is indicated how such structures can provide an efficient means of assessing dielectric planarisation. This provides process engineers with a important, nondestructive means of assessing and monitoring a key technology parameter. The use of three-dimensional simulation in backend process optimisation is briefly described.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116846560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A new test structure to study electromigration at grain boundaries using the single-crystal aluminum interconnection 一种利用单晶铝互连研究晶界电迁移的新型测试结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513977
K. Kusuyama, Y. Nakajima, Y. Murakami
{"title":"A new test structure to study electromigration at grain boundaries using the single-crystal aluminum interconnection","authors":"K. Kusuyama, Y. Nakajima, Y. Murakami","doi":"10.1109/ICMTS.1995.513977","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513977","url":null,"abstract":"The new test structure with single-crystal aluminum interconnection made by the lateral-epitaxial growth method, was designed to study electromigration (EM) at grain boundaries in bamboo structure. Having only two bamboo grain boundaries, the EM mechanism can be analyzed more accurately by this new structure than using the ordinary structure of series of grain boundaries.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"550 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113996554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate capacitor matching measurements using floating gate test structures 使用浮栅测试结构进行精确的电容匹配测量
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513960
H. Tuinhout, H. Elzinga, J.T.H. Brugman, F. Postma
{"title":"Accurate capacitor matching measurements using floating gate test structures","authors":"H. Tuinhout, H. Elzinga, J.T.H. Brugman, F. Postma","doi":"10.1109/ICMTS.1995.513960","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513960","url":null,"abstract":"This paper discusses a new method for characterization of matching of capacitors using the so-called floating gate capacitance measurement method. The paper explains this (DC!!) measurement method and then discusses modifications that were implemented to improve the measurement accuracy and repeatability from its original thousands of ppms (0.1 to 0.3%) to values down to 50 ppm. This improved accuracy is necessary for correct characterization of capacitor matching. The method is demonstrated with results from double-polysilicon capacitor matching measurements.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116338140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
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