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Proceedings International Conference on Microelectronic Test Structures最新文献

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An automatic implementation of dynamic electromigration tests 自动实现动态电迁移测试
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513980
Wei Zhang, Y.H. Cheng, Z.G. Li, W.L. Guo, Y.H. Sun, X.X. Li
{"title":"An automatic implementation of dynamic electromigration tests","authors":"Wei Zhang, Y.H. Cheng, Z.G. Li, W.L. Guo, Y.H. Sun, X.X. Li","doi":"10.1109/ICMTS.1995.513980","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513980","url":null,"abstract":"A computer controlled testing system built up with hp instruments is described for dynamic electromigration characterization under constant and pulsed DC stressing. Two specially designed specimens with built-in temperature sensor are also presented in cooperation with the system. A series of electromigration tests was performed in terms of current, temperature and frequency ramps. Typical experimental results are discussed in this paper.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124381927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology 硬SOI技术的工艺产量和可靠性数据之间的相关性的证据
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513976
V. Riviere, A. Touboul, S. B. Amor, G. Gregoris, J.L. Stevenson, P.S. Yeung
{"title":"Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology","authors":"V. Riviere, A. Touboul, S. B. Amor, G. Gregoris, J.L. Stevenson, P.S. Yeung","doi":"10.1109/ICMTS.1995.513976","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513976","url":null,"abstract":"A methodology for wafer level reliability prediction is described. Accelerated lifetests performed on specifically designed test structures allowed us to correlate reliability with elementary process yields. These elementary yields were extracted for each test structure (which characterizes a process step) from data obtained after wafer level tests. The wafer \"peripheral\" area, on which was detected a significant number of clustered defects at wafer level, presented few failures during the accelerated lifetest, showing that the geographical origin of the devices does not significantly affect the reliability.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Influence of short circuits on data of contact and via open circuits determined by a novel weave test structure 一种新型编织试验结构确定了短路对接触和通断回路数据的影响
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513937
C. Hess, L. Weiland
{"title":"Influence of short circuits on data of contact and via open circuits determined by a novel weave test structure","authors":"C. Hess, L. Weiland","doi":"10.1109/ICMTS.1995.513937","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513937","url":null,"abstract":"The influence that short circuits have on contact hole open circuits and via hole open circuits in regular string test structures will be investigated. To detect open circuits as well as short circuits in adjacent conducting layers of backend process steps, a novel weave test structure (WTS) is presented. Numerous contact strings or via strings are arranged inside boundary pads like a woven piece of cloth. Thus, short circuits between different strings are also electrically detectable.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Depth measurements using alpha particles and upsetable SRAMs 用α粒子和可调ram进行深度测量
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513983
M. Buehler, M. Reier, G. Soli
{"title":"Depth measurements using alpha particles and upsetable SRAMs","authors":"M. Buehler, M. Reier, G. Soli","doi":"10.1109/ICMTS.1995.513983","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513983","url":null,"abstract":"A custom designed SRAM was used to measure the thickness of integrated circuit over layers and the epi-layer thickness using alpha particles and a test SRAM. The over layer consists of oxide, nitride, metal and junction regions.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123633827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test structure and simplified distribution model for identification of base resistance components in self-aligned polysilicon base electrode bipolar transistors 自对准多晶硅基极双极晶体管基极电阻分量识别的测试结构及简化分布模型
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513958
M. Tanabe, H. Shimamoto, T. Onai, K. Washio
{"title":"Test structure and simplified distribution model for identification of base resistance components in self-aligned polysilicon base electrode bipolar transistors","authors":"M. Tanabe, H. Shimamoto, T. Onai, K. Washio","doi":"10.1109/ICMTS.1995.513958","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513958","url":null,"abstract":"A test structure and a simplified distribution base resistance model (SDM) are proposed to identify each component of the base resistance and to obtain the dominant one. This model separates the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124109421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Leak current characterization in high frequency operation of CMOS circuits fabricated on SOI substrate SOI基板CMOS电路高频工作漏电流特性研究
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513947
H. Ito, K. Asada
{"title":"Leak current characterization in high frequency operation of CMOS circuits fabricated on SOI substrate","authors":"H. Ito, K. Asada","doi":"10.1109/ICMTS.1995.513947","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513947","url":null,"abstract":"Threshold voltage shift in high frequency operation of CMOS/SOI is experimentally studied, using supply current measurement of inverter chains as test structures. For a large supply voltage the electron-hole generation current becomes dominant, resulting in a lower threshold voltage, while the threshold voltage becomes higher than the DC case for a low supply voltage. This method will be useful as a measure of \"substrate current\" for floating body CMOS/SOI.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114392305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The charging and discharging of stress-generated traps inside thin silicon oxide 薄氧化硅内部应力生成阱的充放电
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513979
R. S. Scott, D. Dumin
{"title":"The charging and discharging of stress-generated traps inside thin silicon oxide","authors":"R. S. Scott, D. Dumin","doi":"10.1109/ICMTS.1995.513979","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513979","url":null,"abstract":"Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible DC component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside of the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121963550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An in-process monitoring method for electromigration resistance of multilayered metal interconnects 多层金属互连电迁移电阻的过程监测方法
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513951
T. Fujii, T. Itoh, H. Ishizuka, K. Okuyama, K. Kubota
{"title":"An in-process monitoring method for electromigration resistance of multilayered metal interconnects","authors":"T. Fujii, T. Itoh, H. Ishizuka, K. Okuyama, K. Kubota","doi":"10.1109/ICMTS.1995.513951","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513951","url":null,"abstract":"This paper describes it method for monitoring electromigration (EM) resistance of multilayered metal interconnects which have been widely used in recent LSI technologies. We studied the combination of SWEAT (Standard Wafer-Level Electromigration Acceleration Test) patterns and the BEM (Breakdown Energy of Metal) method. We found that SWEAT pattern has a threshold length in its narrow portion to grow voids induced by EM, and optimized the conditions for the BEM method in terms of temperature and ramping rate. We have realized an in-process EM monitoring method which takes 4 minutes per sample at room temperature using the above combination.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127076254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Resistance modeling of test structures for accurate fault detection in backend process steps using a digital tester 测试结构的电阻建模，以便在后端工艺步骤中使用数字测试仪进行准确的故障检测
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513985
C. Hess, L. Weiland
{"title":"Resistance modeling of test structures for accurate fault detection in backend process steps using a digital tester","authors":"C. Hess, L. Weiland","doi":"10.1109/ICMTS.1995.513985","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513985","url":null,"abstract":"A methodology is presented to enable the usage of a digital tester for an accurate detection of open circuits as well as short circuits in test structures to control backend process steps. Therefore, a novel graph model will be introduced to calculate the resistance values of test structures containing defects. The paper gives a comprehensive description of the procedure to adjust the tester parameters to those test structures.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Influence of tilted high-energy ion-implantation upon scaled CMOS structure 倾斜高能离子注入对CMOS结构的影响
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513982
H. Takatsuka, H. Sato, T. Izawa, T. Hisaeda, H. Goto, S. Kawamura
{"title":"Influence of tilted high-energy ion-implantation upon scaled CMOS structure","authors":"H. Takatsuka, H. Sato, T. Izawa, T. Hisaeda, H. Goto, S. Kawamura","doi":"10.1109/ICMTS.1995.513982","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513982","url":null,"abstract":"Retrograde well needs a thick resist mask and ions should be implanted into a wafer at a tilt angle to minimize channeling, therefore, \"mask edge shadowing\" becomes serious. We evaluated the influence of the angle of ion-implantation on Vth shifts of MOSFETs when source/drain-well spacing becomes small. It is known that when the nsd-nwell spacing becomes small, nwell impurities diffuse laterally to NMOS channel regions. That causes Vth lowering. But we found out a new phenomenon that Vth rises when the nsd-pwell spacing becomes small. That is caused by penetration of high-energy ions for well formation through the mask edge. The angle of ion-implantation for the well formation is influential on Vth of MOSFETs nearby the mask edge. The ion-implantation at 0/spl deg/ tilt angle is desired.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126060747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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