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Proceedings International Conference on Microelectronic Test Structures最新文献

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Characterization and modeling of MOS mismatch in analog CMOS technology 模拟CMOS技术中MOS失配的表征与建模
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513967
Shyh-Chyi Wong, J. Ting, S. Hsu
{"title":"Characterization and modeling of MOS mismatch in analog CMOS technology","authors":"Shyh-Chyi Wong, J. Ting, S. Hsu","doi":"10.1109/ICMTS.1995.513967","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513967","url":null,"abstract":"This paper studies the mismatch characteristics in CMOS technology for precision analog design. Mismatch of MOS devices is investigated. The impact of layout-configuration and device-size are characterized. For clean mismatch measurement, a differential method of extracting mismatch parameters is developed. An empirical model is further proposed for simulating mismatch behavior in SPICE.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123013824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs 一种确定亚微米LDD mosfet的冶金栅源极/漏极重叠长度的电容方法
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513963
M. Jo, Jin-Hyoung Kim, Sung-Ki Kim, H. Yoon, Dai-Hoon Lee
{"title":"A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs","authors":"M. Jo, Jin-Hyoung Kim, Sung-Ki Kim, H. Yoon, Dai-Hoon Lee","doi":"10.1109/ICMTS.1995.513963","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513963","url":null,"abstract":"A new CV method is proposed to determine the metallurgical gate-to-source/drain overlap length of LDD MOSFETs. In addition, the flatband voltage is extracted roughly by using the same method. The gate-to-substrate capacitances of a plate gate capacitor and finger type capacitor with the same total gate areas are measured with varying gate bias. At the peak point of difference between the two capacitor data, overlap length is extracted using a simple formula. This method is evaluated using the two-dimensional device simulator.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117064601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics 由闪存读扰特性导出的隧道氧化物应力诱发漏电流
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513953
S. Satoh, G. Hemink, F. Hatakeyama, S. Aritome
{"title":"Stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics","authors":"S. Satoh, G. Hemink, F. Hatakeyama, S. Aritome","doi":"10.1109/ICMTS.1995.513953","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513953","url":null,"abstract":"This paper describes the characteristics of the stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items are newly observed. First, the threshold voltage shift (/spl Delta/Vth) of the memory cell under gate stress condition (read disturb condition) consists of two regions, a decay region and a steady state region. The decay region is due to both the initial trapping or detrapping of carriers in the tunnel oxide and the decay of the stress induced leakage current of the tunnel oxide. The steady state region is determined by the saturation of the stress induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high temperature (125/spl deg/C) write/erase operation degrades the steady state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123748038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new hierarchical RSM for TCAD-based device design to predict CMOS development 一种新的基于tcad的器件设计分层RSM，用于预测CMOS的发展
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513991
H. Sato, K. Tsuneno, K. Aoyama, T. Nakamura, H. Kunitomo, H. Masuda
{"title":"A new hierarchical RSM for TCAD-based device design to predict CMOS development","authors":"H. Sato, K. Tsuneno, K. Aoyama, T. Nakamura, H. Kunitomo, H. Masuda","doi":"10.1109/ICMTS.1995.513991","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513991","url":null,"abstract":"A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM (Response Surface Method) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process/device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01 V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Measurement of patterned film linewidth for interconnect characterization 互连表征用图像化薄膜线宽的测量
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513939
L. W. Linholm, R. Allen, M. Cresswell, R. Ghoshtagore, S. Mayo, H. Schafft, J. Kramar, E. Teague
{"title":"Measurement of patterned film linewidth for interconnect characterization","authors":"L. W. Linholm, R. Allen, M. Cresswell, R. Ghoshtagore, S. Mayo, H. Schafft, J. Kramar, E. Teague","doi":"10.1109/ICMTS.1995.513939","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513939","url":null,"abstract":"Test results from high-quality electrical and physical measurements on the same cross-bridge resistor test structure with approximately vertical sidewalls have shown differences in linewidth as great as 90 nm for selected conductive films. These differences were independent of design linewidth. As dimensions become smaller, the accurate measurement of the patterned conductor width is necessary to assure predictable timing performance of the interconnect system as well as control of critical device parameters.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129292028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Characterization of density of trap states at the back interface of SIMOX wafers SIMOX晶圆后界面阱态密度的表征
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513949
A. Takubo, T. Hanajiri, T. Sugano, K. Kajiyama
{"title":"Characterization of density of trap states at the back interface of SIMOX wafers","authors":"A. Takubo, T. Hanajiri, T. Sugano, K. Kajiyama","doi":"10.1109/ICMTS.1995.513949","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513949","url":null,"abstract":"We measured the density of the trap states at the interface of SIMOX (Separation by Implanted Oxygen) wafers by high frequency C-V measurements of MOS diodes fabricated on SIMOX wafers. SIMOX structures with p-type or n-type silicon substrates are found to have traps of about 10/sup 12/ cm/sup -2/ eV/sup -1/ at the back interface. We tried to estimate the density of the trap states at the front interface, too.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gate antenna structures for monitoring oxide quality and reliability 用于监测氧化物质量和可靠性的栅极天线结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513952
S. Nariani, C. Gabriel, D. Pramanik, K. Ng
{"title":"Gate antenna structures for monitoring oxide quality and reliability","authors":"S. Nariani, C. Gabriel, D. Pramanik, K. Ng","doi":"10.1109/ICMTS.1995.513952","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513952","url":null,"abstract":"Gate antenna structures have been developed to detect charge induced process damage to sub-micron gate oxide. For the first time, this damage is correlated with product failure due to gate oxide in accelerated life testing. These antenna structures are thus proven to be useful for wafer level gate oxide reliability screening.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127005232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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