A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs

Abstract

A new CV method is proposed to determine the metallurgical gate-to-source/drain overlap length of LDD MOSFETs. In addition, the flatband voltage is extracted roughly by using the same method. The gate-to-substrate capacitances of a plate gate capacitor and finger type capacitor with the same total gate areas are measured with varying gate bias. At the peak point of difference between the two capacitor data, overlap length is extracted using a simple formula. This method is evaluated using the two-dimensional device simulator.