Characterization and modeling of MOS mismatch in analog CMOS technology

Abstract

This paper studies the mismatch characteristics in CMOS technology for precision analog design. Mismatch of MOS devices is investigated. The impact of layout-configuration and device-size are characterized. For clean mismatch measurement, a differential method of extracting mismatch parameters is developed. An empirical model is further proposed for simulating mismatch behavior in SPICE.