A. Toffoli, J. Pelloie, O. Faynot, C. Raynaud, B. Giffard, J. Hartmann
{"title":"Accurate determination of the main parameters from V/sub t/(V/sub b/) curves of fully-depleted SOI devices","authors":"A. Toffoli, J. Pelloie, O. Faynot, C. Raynaud, B. Giffard, J. Hartmann","doi":"10.1109/ICMTS.1995.513948","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513948","url":null,"abstract":"This paper describes a simple and accurate method to extract the main technological parameters: buried oxide thickness, silicon film thickness and doping level which are used to design fully-depleted SOI devices. Both enhancement-mode and accumulation-mode devices are measured for different silicon thicknesses from 200 to 500 /spl Aring/, the parameters are extracted from the variation of the front threshold voltage with the back gate bias using the corresponding analytical models.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"United methodology for pre-determination of bipolar transistor SPICE model parameters for low, middle and high power ICs","authors":"K. O. Petrosjanc, I. Kharitonov, N.I. Rjabov","doi":"10.1109/ICMTS.1995.513975","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513975","url":null,"abstract":"To minimize measurement efforts a united methodology is proposed for getting SPICE model parameters for low, middle and high power bipolar devices with arbitrary layouts. The standard test structure technique is connected with the using of universal software tools for resistance numerical calculation. This approach is effectively applicable to the complex analog and/or digital ICs which are yet to be fabricated.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115751211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Pergoot, B. Graindourze, E. Janssens, J. Bastos, M. Steyaert, P. Kinget, R. Roovers, W. Sansen
{"title":"Statistics for matching","authors":"A. Pergoot, B. Graindourze, E. Janssens, J. Bastos, M. Steyaert, P. Kinget, R. Roovers, W. Sansen","doi":"10.1109/ICMTS.1995.513971","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513971","url":null,"abstract":"A statistical approach for evaluating the stochastic mismatching between two identically designed elements on the same chip is discussed. An approach to determine accurate matching parameters for a specific pair of devices and to obtain realistic worst case parameters for the area dependency model is presented. The approach is demonstrated by applying it to measured transistor threshold voltage mismatching data for a 0.7 /spl mu/m CMOS technology.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122702554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Understanding clustering of defects in a sub-0.5 /spl mu/m CMOS fabricator","authors":"A. Satya","doi":"10.1109/ICMTS.1995.513990","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513990","url":null,"abstract":"Over two decades of bipolar-experience has previously alerted one to the fact that the extent of defect clustering, assumed in the CMOS yield models, may not hold for defects monitored on microelectronic test structures (MTS). Tracing the defect clustering from inline CMOS MTS, we now describe a viable yield prediction model using data from the various inline monitors, which also helps reconcile the questions raised earlier. Such a yield-bridge between the MTS-data and the product yield establishes the validity of the yield model and assumptions therein.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124696201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Conti, S. Orcioni, C. Turchetti, P. Bellutti, M. Zen, N. Zorzi, G. Soncini
{"title":"An efficient method to predict drain current dispersion in MOS transistors from technological parameters fluctuations","authors":"M. Conti, S. Orcioni, C. Turchetti, P. Bellutti, M. Zen, N. Zorzi, G. Soncini","doi":"10.1109/ICMTS.1995.513974","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513974","url":null,"abstract":"This paper proposes an empirical MOSFET model, supported by statistically significant data derived from measurements on test-structures. The model, due to its accuracy, can be useful in predicting \"a priori\" fabrication process tolerances on ICs performances and in carrying out a combined \"process-circuit\" performances optimization.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132038937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A test structure for the measurement of fast internal signals in CMOS VLSI circuits","authors":"B. Laquai, H. Richter, B. Hoefflinger","doi":"10.1109/ICMTS.1995.513943","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513943","url":null,"abstract":"A test structure and a measurement method were developed allowing the analog measurement of fast signals at internal circuit nodes. The measurement method is based on the sampling principle. The test structure acts as a sampling probe integrated on chip. Attached to a circuit node, the probe imposes an additional load of only one minimum NMOS transistor gate. The test structure is clocked synchronously with the signal to be measured and converts the voltage for a fixed sampling point into a DC current. Successive DC measurements are taken while shifting the phase of the sampling clock relative to the system clock. The voltage signal is reconstructed by comparison of the sampled current values with reference values for a known input voltage.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122715493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non-destructive method of shear stress test by new test structure","authors":"H. Matsushima, T. Wada","doi":"10.1109/ICMTS.1995.513938","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513938","url":null,"abstract":"A new test structure was developed for a nondestructive method. The purpose of this test structure is to detect the influence of thermomechanical stress between silicon chip and plastic resin. In this structure, detection of the failure is very easy, because the influence of thermomechanical stress can be detected electrically. By using this new structure, the following results were found: (1) Dependence on chip size; (2) Influence of layout of package; (3) Acceleration between heat shock and temperature cycle tests.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116674828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kokawa, M. Kimura, M. Kume, H. Yamamoto, A. Koyama
{"title":"Test structures for the evaluation of Si substrates","authors":"Y. Kokawa, M. Kimura, M. Kume, H. Yamamoto, A. Koyama","doi":"10.1109/ICMTS.1995.513950","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513950","url":null,"abstract":"The quality of Si substrates affecting the oxide reliability was investigated using various kinds of test structures like flat capacitor, field edge array and gate edge array. The field edge array test structure which resembles the conditions found for a real device is shown to be quite effective to determine the quality of oxides. Oxide grown on a P type epitaxial layer on P/sup +/ silicon substrate shows highest reliability in all test structures. Gettering of heavy metals and/or crystal defects by the P/sup +/ silicon substrate is the dominant mechanism for the improvement of the oxide reliability.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114299479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test structure for determining the charge distribution in the oxide of MOS structure","authors":"Y. Takahashi, S. Imaki, K. Ohnishi, M. Yoshikawa","doi":"10.1109/ICMTS.1995.513981","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513981","url":null,"abstract":"We propose a measurement method to obtain the charge distribution in the oxide layer of a MOS structure. We obtain various oxide thicknesses by gradually varying the etching time of the oxide layer (slanted etching). Using this method, we have determined the charge distribution in the oxide layer of MOS structures before and after ammonia annealing by measuring the mid-gap voltages of C-V curves.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114812060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new extraction method for unit bipolar junction transistor capacitance parameters","authors":"N. Gambetta, B. Cialdella, D. Céli, M. Depey","doi":"10.1109/ICMTS.1995.513965","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513965","url":null,"abstract":"A new method for extracting the area, peripheral and corner capacitance components of bipolar junction transistor, using measurements versus bias on a number of different structures is presented and validated. The same model with different parameters is used for the three components. Validation has been made using a quasi-2D simulator. Finally, it is shown that this method gives accurate results regarding the goodness of fit.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124124162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}