Understanding clustering of defects in a sub-0.5 /spl mu/m CMOS fabricator

Abstract

Over two decades of bipolar-experience has previously alerted one to the fact that the extent of defect clustering, assumed in the CMOS yield models, may not hold for defects monitored on microelectronic test structures (MTS). Tracing the defect clustering from inline CMOS MTS, we now describe a viable yield prediction model using data from the various inline monitors, which also helps reconcile the questions raised earlier. Such a yield-bridge between the MTS-data and the product yield establishes the validity of the yield model and assumptions therein.