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Proceedings International Conference on Microelectronic Test Structures最新文献

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Soft error immunity of 1-Volt CMOS memory cells with MTCMOS technology 采用MTCMOS技术的1伏CMOS存储单元的软误差抗扰性
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513955
T. Douseki, S. Mutoh, T. Ueki, J. Yamada
{"title":"Soft error immunity of 1-Volt CMOS memory cells with MTCMOS technology","authors":"T. Douseki, S. Mutoh, T. Ueki, J. Yamada","doi":"10.1109/ICMTS.1995.513955","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513955","url":null,"abstract":"Soft error immunity of a 1-V operating CMOS memory cell is described. A test chip using multi threshold CMOS (MTCMOS) technology is fabricated and the immunity of the memory cell is evaluated. It is demonstrated that a full CMOS memory cell has high immunity at 1-V operation.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132857720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wafer mapping using DOE and RSM techniques 使用DOE和RSM技术进行晶圆映射
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513989
A. J. Walton, M. Fallon, D. Wilson
{"title":"Wafer mapping using DOE and RSM techniques","authors":"A. J. Walton, M. Fallon, D. Wilson","doi":"10.1109/ICMTS.1995.513989","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513989","url":null,"abstract":"This paper applies classical DOE techniques to the the selection of measurement points for wafer mapping. RSM is used to generate the contour plots and it is shown that in many cases transformations can be used to improve the accuracy of wafer maps.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Defect parameter extraction in backend process steps using a multilayer checkerboard test structure 采用多层棋盘测试结构进行后端工艺步骤缺陷参数提取
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513944
C. Hess, L. Weiland
{"title":"Defect parameter extraction in backend process steps using a multilayer checkerboard test structure","authors":"C. Hess, L. Weiland","doi":"10.1109/ICMTS.1995.513944","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513944","url":null,"abstract":"To control defect appearance in numerous conducting layers of backend process steps, a novel multilayer checkerboard test structure (MCTS) is presented. The separation and localization of defects-causing electrically detectable intralayer short circuits as well as interlayer short circuits-is achieved by dividing the chip area into distinguishable small subchips inside given standard boundary pads without using any active semiconductor devices. The precise localization facilitates a versatile optical defect parameter extraction.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132319879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Electrical characteristics of CMOSFETs with gates crossing source/drain regions at 90/spl deg/ and 45/spl deg/ 栅极在90/声压角和45/声压角下穿过源极/漏极的cmosfet的电特性
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513970
T. Ohzone, N. Matsuyama
{"title":"Electrical characteristics of CMOSFETs with gates crossing source/drain regions at 90/spl deg/ and 45/spl deg/","authors":"T. Ohzone, N. Matsuyama","doi":"10.1109/ICMTS.1995.513970","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513970","url":null,"abstract":"The electrical characteristics of scaled CMOSFETs with gates crossing sources/drains at 90/spl deg/ and 45/spl deg/ are experimentally investigated using test devices fabricated by an n-well CMOS process with trench-isolation. The gain factors and the saturation drain-currents of n-MOSFETs are estimated by a simple correction theory which is derived by combining a center MOSFET and two edge MOSFETs. However, relatively large differences between the theoretical values and the experimental results are observed in p-MOSFETs with narrower widths less than the channel length. Other basic device parameters such as threshold voltages and subthreshold swings are qualitatively explained by the impurity profiles along the channel width direction, bird's beaks formed at the isolation-edges, and the change of channel length for narrow width 45/spl deg/ MOSFETs.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122959064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The Wheatstone bridge as an alignment test structure 惠斯通桥作为校准测试结构
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513940
U. Kaempf
{"title":"The Wheatstone bridge as an alignment test structure","authors":"U. Kaempf","doi":"10.1109/ICMTS.1995.513940","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513940","url":null,"abstract":"A new test structure for the electrical measurement of level-to-level registration is introduced. This structure, based on the Wheatstone bridge measurement principle, offers improved accuracy over the conventional U-shaped test structure. With the described Wheatstone bridge method, the registration error (misalignment) is directly proportional to a single voltage. In contrast, the misalignment of the U-shaped structure is calculated from the difference of two voltages, an operation that can result in poor precision. The paper describes a two-by-twelve contact pad module, which includes two Wheatstone bridge structures to measure the misalignment in the X- and Y-directions, two calibration structures to determine the zero- and full-scale accuracy, and a Van der Pauw structure to measure the sheet resistance of the conducting material as required for the alignment measurement. The mathematical expressions are derived, and actual test results are discussed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128351307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Characterization and modeling of transistors embedded in a high performance bipolar logic array 嵌入在高性能双极逻辑阵列中的晶体管的特性和建模
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513969
E. H. Tyler
{"title":"Characterization and modeling of transistors embedded in a high performance bipolar logic array","authors":"E. H. Tyler","doi":"10.1109/ICMTS.1995.513969","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513969","url":null,"abstract":"A set of high-frequency test structures for device characterization and the extraction of DC, CV, and AC bipolar SPICE model parameters has been implemented on a triple layer metal, high-performance bipolar logic array. These structures have proven useful in the development of accurate, statistically based SPICE models, relying on a readily available bank of logic array product base wafers. Sample results and the use of Hewlett-Packard's IC-CAP parameter extraction program to study these structures are discussed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125220813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Use of SPIDER for the identification and analysis of process induced damage in 0.35 /spl mu/m transistors 利用SPIDER对0.35 /spl mu/m晶体管的工艺损伤进行识别和分析
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513935
P. Aum, Xiaoyu Li, V. Prabhakar, T. Brożek, C. Viswanathan
{"title":"Use of SPIDER for the identification and analysis of process induced damage in 0.35 /spl mu/m transistors","authors":"P. Aum, Xiaoyu Li, V. Prabhakar, T. Brożek, C. Viswanathan","doi":"10.1109/ICMTS.1995.513935","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513935","url":null,"abstract":"The paper presents a case study of the use of the SEMATECH SPIDER test structure to evaluate and identify critical damage producing plasma process steps in the fabrication of n- and p-MOS devices manufactured with a 0.35 /spl mu/m CMOS line with 6.5 nm oxide. Electrical characterization of transistor modules enabled the identification of contact etch step as the principal damage producing step for the technology under investigation. The results on HC reliability degradation in CMOS devices are in agreement with the direct observations of oxide degradation, showing that the nature of the damage is of the charging type.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130810554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Mismatch characterization of small size MOS transistors 小尺寸MOS晶体管的失配特性
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513986
J. Bastos, M. Steyaert, R. Roovers, P. Kinget, Willy Sansen, B. Graindourze, A. Pergoot, E. Janssens
{"title":"Mismatch characterization of small size MOS transistors","authors":"J. Bastos, M. Steyaert, R. Roovers, P. Kinget, Willy Sansen, B. Graindourze, A. Pergoot, E. Janssens","doi":"10.1109/ICMTS.1995.513986","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513986","url":null,"abstract":"A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126546593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
Reliability evaluation of thin gate oxide using a flat capacitor test structure 采用扁平电容测试结构的薄栅氧化物可靠性评估
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513954
M. Katsumata, J. Mitsuhashi, K. Kobayashi, Y. Mashiko, H. Koyama
{"title":"Reliability evaluation of thin gate oxide using a flat capacitor test structure","authors":"M. Katsumata, J. Mitsuhashi, K. Kobayashi, Y. Mashiko, H. Koyama","doi":"10.1109/ICMTS.1995.513954","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513954","url":null,"abstract":"A test structure with very low-level current measurement technique (minimum detectable current is 5/spl times/10/sup -17/ A) has been developed and is used for measuring very small change of leakage current caused by trapping and detrapping of electrons or holes. The present technique to measure very low level current of aA order is very useful for accurate evaluation of retention characteristics and stress induced degradation of gate oxide.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-chip measurement of interconnect capacitances in a CMOS process 在CMOS工艺中互连电容的片上测量
Proceedings International Conference on Microelectronic Test Structures Pub Date : 1995-03-22 DOI: 10.1109/ICMTS.1995.513962
A. Khalkhal, P. Nouet
{"title":"On-chip measurement of interconnect capacitances in a CMOS process","authors":"A. Khalkhal, P. Nouet","doi":"10.1109/ICMTS.1995.513962","DOIUrl":"https://doi.org/10.1109/ICMTS.1995.513962","url":null,"abstract":"A new Test Structure for measurement of small constant capacitances is presented. As compared to previously published methods, improvements are obtained in the field of accuracy and resolution. No reference elements are used and the calculated capacitance is free of parasitic capacitance influence. Moreover, the Test Structure occupies a small area. It is particularly suitable for spatial scattering studies and for modelling of small dimension interconnect capacitances.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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